Lines Matching refs:BIT_1S
79 #define BIT_1S (1 << 1) macro
184 #define PCI_MEMEN BIT_1S /* Memory Space Access enable */
817 #define CS_RST_CLR BIT_1S /* Clear Software reset */
822 #define LED_STAT_ON BIT_1S /* Status LED on */
908 #define CFG_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */
930 #define LD_T_STEP BIT_1S /* Decrement FPROM addr. Counter */
940 #define TIM_STOP BIT_1S /* Stop Timer */
948 #define TIM_T_OFF BIT_1S /* Test mode off */
958 #define DPT_START BIT_1S /* Start Descriptor Poll Timer */
971 #define TST_CFG_WRITE_ON BIT_1S /* Enable Config Reg WR */
979 #define TST_FRC_APERR_1M64 BIT_1S /* AddrPERR on 1. phase */
1030 #define I2C_DATA BIT_1S /* I2C Data Port */
1041 #define BSC_START BIT_1S /* Start Blink Source Counter */
1050 #define BSC_T_OFF BIT_1S /* Test mode off */
1064 #define RI_RST_CLR BIT_1S /* Clear RAM Interface Reset */
1071 #define RI_T_OFF BIT_1S /* Timeout Timer Test Off */
1079 #define MA_RST_CLR BIT_1S /* Clear MAC Arbiter Reset */
1090 #define MA_ENA_REC_RX1 BIT_1S /* Enable Recovery Timer RX1 */
1108 #define PA_RST_CLR BIT_1S /* Clear MAC Arbiter Reset */
1133 #define RX1_T_OFF BIT_1S /* RX1 Timeout/Recv Timer Tst Off */
1152 #define TXA_ENA_ARB BIT_1S /* Enable Tx Arbiter */
1161 #define TXA_LIM_T_OFF BIT_1S /* Tx Arb Limit Timer Test Off */
1240 #define SM_TEST_OFF BIT_1S /* Go off the Test Mode */
1279 #define RB_PC_T_OFF BIT_1S /* Packet Counter Tst Off */
1289 #define RB_RP_T_OFF BIT_1S /* Read Pointer Test Off */
1298 #define RB_RST_CLR BIT_1S /* Clear RAM Buf STM Reset */
1332 #define MFF_CLR_INTIST BIT_1S /* Clear IRQ No Time Stamp */
1352 #define MFF_CLR_MAC_RST BIT_1S /* Clear XMAC Reset */
1365 #define MFF_PC_T_OFF BIT_1S /* Packet Counter Test Off */
1376 #define MFF_RP_T_OFF BIT_1S /* Read Pointer Test Off */
1384 #define MFF_RST_CLR BIT_1S /* Clear MAC FIFO Reset */
1395 #define LED_STOP BIT_1S /* Stop Timer */
1404 #define LED_T_OFF BIT_1S /* LED Counter Test mode Off */
1413 #define LED_ON BIT_1S /* switch LED on */
1470 #define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */
1553 #define GMLC_RST_CLR BIT_1S /* Clear GMAC Link Reset */
1575 #define WOL_CTL_ENA_PATTERN_UNIT BIT_1S