441 #define PutByte(reg,value) outb((value), ioaddr+(reg))  macro
504     PutByte(XIRCREG2_GPR2, 0x04|0); /* drive MDCK low */  in mii_idle()
506     PutByte(XIRCREG2_GPR2, 0x04|1); /* and drive MDCK high */  in mii_idle()
518 	PutByte(XIRCREG2_GPR2, 0x0c|2|0); /* set MDIO */  in mii_putbit()
520 	PutByte(XIRCREG2_GPR2, 0x0c|2|1); /* and drive MDCK high */  in mii_putbit()
523 	PutByte(XIRCREG2_GPR2, 0x0c|0|0); /* clear MDIO */  in mii_putbit()
525 	PutByte(XIRCREG2_GPR2, 0x0c|0|1); /* and drive MDCK high */  in mii_putbit()
551     PutByte(XIRCREG2_GPR2, 4|0); /* drive MDCK low */  in mii_getbit()
554     PutByte(XIRCREG2_GPR2, 4|1); /* drive MDCK high again */  in mii_getbit()
1327 	PutByte(XIRCREG_CR, 0);  in xirc2ps_interrupt()
1347     PutByte(XIRCREG40_RXST0, (~rx_status & 0xff));  in xirc2ps_interrupt()
1350     PutByte(XIRCREG40_TXST0, 0);  in xirc2ps_interrupt()
1351     PutByte(XIRCREG40_TXST1, 0);  in xirc2ps_interrupt()
1464 	PutByte(XIRCREG_CR, ClearRxOvrun);  in xirc2ps_interrupt()
1485 	PutByte(XIRCREG_CR, RestartTx);  /* restart transmitter process */  in xirc2ps_interrupt()
1520     PutByte(XIRCREG_CR, EnableIntr);  /* re-enable interrupts */  in xirc2ps_interrupt()
1586 	PutByte(XIRCREG_EDP, skb->data[pktlen-1]);  in do_start_xmit()
1589 	PutByte(XIRCREG_CR, TransmitPacket|EnableIntr);  in do_start_xmit()
1641 	    PutByte(j, addr[5-i]);  in set_addresses()
1643 	    PutByte(j, addr[i]);  in set_addresses()
1661 	PutByte(XIRCREG42_SWC1, 0x06); /* set MPE and PME */  in set_multicast_list()
1663 	PutByte(XIRCREG42_SWC1, 0x06); /* set MPE */  in set_multicast_list()
1666 	PutByte(XIRCREG42_SWC1, 0x00);  in set_multicast_list()
1668 	PutByte(XIRCREG40_CMD0, Offline);  in set_multicast_list()
1671 	PutByte(XIRCREG40_CMD0, EnableRecv | Online);  in set_multicast_list()
1673 	PutByte(XIRCREG42_SWC1, 0x00);  in set_multicast_list()
1780     PutByte(XIRCREG4_GPR1, 0);	     /* clear bit 0: power down */  in hardreset()
1783 	PutByte(XIRCREG4_GPR1, 1);	 /* set bit 0: power up */  in hardreset()
1785 	PutByte(XIRCREG4_GPR1, 1 | 4);	 /* set bit 0: power up, bit 2: AIC */  in hardreset()
1799     PutByte(XIRCREG_CR, SoftReset); /* set */  in do_reset()
1801     PutByte(XIRCREG_CR, 0);	     /* clear */  in do_reset()
1809 	PutByte(XIRCREG4_GPR0, 0x0e);  in do_reset()
1822 	    PutByte(XIRCREG4_GPR0, 4);  in do_reset()
1827 	PutByte(XIRCREG42_SWC1, 0xC0);  in do_reset()
1830 	PutByte(XIRCREG42_SWC1, 0x80);  in do_reset()
1844     PutByte(XIRCREG1_IMR0, 0xff); /* allow all ints */  in do_reset()
1845     PutByte(XIRCREG1_IMR1, 1	); /* and Set TxUnderrunDetect */  in do_reset()
1850     PutByte(XIRCREG1_ECR, value);  in do_reset()
1855     PutByte(XIRCREG42_SWC0, 0x20); /* disable source insertion */  in do_reset()
1879     PutByte(XIRCREG40_RMASK0, 0xff); /* ROK, RAB, rsv, RO, CRC, AE, PTL, MP */  in do_reset()
1880     PutByte(XIRCREG40_TMASK0, 0xff); /* TOK, TAB, SQE, LL, TU, JAB, EXC, CRS */  in do_reset()
1881     PutByte(XIRCREG40_TMASK1, 0xb0); /* rsv, rsv, PTD, EXT, rsv,rsv,rsv, rsv*/  in do_reset()
1882     PutByte(XIRCREG40_RXST0,  0x00); /* ROK, RAB, REN, RO, CRC, AE, PTL, MP */  in do_reset()
1883     PutByte(XIRCREG40_TXST0,  0x00); /* TOK, TAB, SQE, LL, TU, JAB, EXC, CRS */  in do_reset()
1884     PutByte(XIRCREG40_TXST1,  0x00); /* TEN, rsv, PTD, EXT, retry_counter:4  */  in do_reset()
1890 	    PutByte(XIRCREG2_MSR, GetByte(XIRCREG2_MSR) | 0x08);  in do_reset()
1897 		PutByte(XIRCREG42_SWC1, 0xC0);  in do_reset()
1899 		PutByte(XIRCREG42_SWC1, 0x80);  in do_reset()
1903 	    PutByte(XIRCREG1_ECR, GetByte(XIRCREG1_ECR | FullDuplex));  in do_reset()
1913 	PutByte(XIRCREG2_LED, 0x3b);  in do_reset()
1915 	PutByte(XIRCREG2_LED, 0x3a);  in do_reset()
1918 	PutByte(0x0b, 0x04); /* 100 Mbit LED */  in do_reset()
1923 	PutByte(XIRCREG40_CMD0, EnableRecv | Online);  in do_reset()
1928     PutByte(XIRCREG1_IMR0, 0xff);  in do_reset()
1931     PutByte(XIRCREG_CR, EnableIntr);  in do_reset()
1934 	    PutByte(0x10, 0x11); /* unmask master-int bit */  in do_reset()
2032     PutByte(XIRCREG4_GPR1, 0);	     /* clear bit 0: power down */  in do_powerdown()
2051     PutByte(XIRCREG_CR, 0);  /* disable interrupts */  in do_stop()
2053     PutByte(XIRCREG1_IMR0, 0x00); /* forbid all ints */  in do_stop()
2055     PutByte(XIRCREG4_GPR1, 0);	/* clear bit 0: power down */  in do_stop()