Lines Matching refs:write_scc
255 static void write_scc(struct scc_priv *priv, int reg, int val);
335 write_scc(&info->priv[0], R9, FHWRES); in cleanup_module()
499 write_scc(priv, R9, FHWRES | MIE | NV); in setup_adapter()
502 write_scc(priv, R15, SHDLCE); in setup_adapter()
517 write_scc(priv, R15, 0); in setup_adapter()
530 write_scc(priv, R15, CTSIE); in setup_adapter()
531 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
532 write_scc(priv, R1, EXT_INT_ENAB); in setup_adapter()
547 write_scc(priv, R1, 0); in setup_adapter()
548 write_scc(priv, R15, 0); in setup_adapter()
549 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
622 static void write_scc(struct scc_priv *priv, int reg, int val) { in write_scc() function
751 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_open()
753 write_scc(priv, R4, SDLC | X1CLK); in scc_open()
755 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in scc_open()
757 write_scc(priv, R3, Rx8); in scc_open()
759 write_scc(priv, R5, Tx8); in scc_open()
761 write_scc(priv, R6, 0); in scc_open()
763 write_scc(priv, R7, FLAG); in scc_open()
767 write_scc(priv, R15, SHDLCE); in scc_open()
769 write_scc(priv, R7, AUTOEOM); in scc_open()
770 write_scc(priv, R15, 0); in scc_open()
774 write_scc(priv, R15, SHDLCE); in scc_open()
795 if (priv->type == TYPE_TWIN) write_scc(priv, R7, AUTOEOM | TXFIFOE); in scc_open()
796 else write_scc(priv, R7, AUTOEOM); in scc_open()
798 write_scc(priv, R7, AUTOEOM | RXFIFOH); in scc_open()
800 write_scc(priv, R15, 0); in scc_open()
804 write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ)); in scc_open()
809 write_scc(priv, R12, priv->param.brg_tc & 0xFF); in scc_open()
810 write_scc(priv, R13, (priv->param.brg_tc>>8) & 0xFF); in scc_open()
813 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL); in scc_open()
815 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL); in scc_open()
818 write_scc(priv, R14, DTRREQ | BRSRC); in scc_open()
828 write_scc(priv, R11, priv->param.clocks); in scc_open()
847 write_scc(priv, R15, DCDIE); in scc_open()
870 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_close()
933 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8); in scc_send_packet()
934 write_scc(priv, R15, 0); in scc_send_packet()
976 write_scc(&info->priv[0], R0, RES_H_IUS); in z8530_isr()
1024 write_scc(priv, R0, ERR_RES); in rx_isr()
1053 if (priv->param.dma < 0) write_scc(priv, R0, ERR_RES); in special_condition()
1152 write_scc(priv, R0, RES_Tx_P); in tx_isr()
1163 write_scc(priv, R0, RES_EOM_L); in tx_isr()
1182 write_scc(priv, R15, TxUIE); in tx_on()
1188 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN | WT_RDY_ENAB); in tx_on()
1197 write_scc(priv, R15, TxUIE); in tx_on()
1198 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN | TxINT_ENAB); in tx_on()
1202 if (priv->chip == Z8530) write_scc(priv, R0, RES_EOM_L); in tx_on()
1226 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx | in rx_on()
1232 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT | in rx_on()
1235 write_scc(priv, R0, ERR_RES); in rx_on()
1236 write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB); in rx_on()
1242 write_scc(priv, R3, Rx8); in rx_off()
1247 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in rx_off()
1259 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1281 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); in es_isr()
1287 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1288 write_scc(priv, R0, RES_EXT_INT); in es_isr()
1300 write_scc(priv, R15, 0); in es_isr()
1318 write_scc(priv, R15, 0); in es_isr()
1326 write_scc(priv, R15, 0); in es_isr()
1347 write_scc(priv, R5, TxCRC_ENAB | Tx8); in tm_isr()
1349 if (priv->type != TYPE_TWIN) write_scc(priv, R15, 0); in tm_isr()
1353 write_scc(priv, R15, DCDIE); in tm_isr()
1368 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8); in tm_isr()
1369 write_scc(priv, R15, 0); in tm_isr()
1373 if (priv->type != TYPE_TWIN) write_scc(priv, R15, DCDIE); in tm_isr()
1378 write_scc(priv, R15, DCDIE); in tm_isr()
1406 write_scc(priv, R15, r15 | CTSIE); in start_timer()