Lines Matching refs:iobase

18 #define EWRK3_CSR    iobase+0x00   /* Control and Status Register */
19 #define EWRK3_CR     iobase+0x01   /* Control Register */
20 #define EWRK3_ICR    iobase+0x02   /* Interrupt Control Register */
21 #define EWRK3_TSR    iobase+0x03   /* Transmit Status Register */
22 #define EWRK3_RSVD1  iobase+0x04   /* RESERVED */
23 #define EWRK3_RSVD2  iobase+0x05   /* RESERVED */
24 #define EWRK3_FMQ    iobase+0x06   /* Free Memory Queue */
25 #define EWRK3_FMQC   iobase+0x07   /* Free Memory Queue Counter */
26 #define EWRK3_RQ     iobase+0x08   /* Receive Queue */
27 #define EWRK3_RQC    iobase+0x09   /* Receive Queue Counter */
28 #define EWRK3_TQ     iobase+0x0a   /* Transmit Queue */
29 #define EWRK3_TQC    iobase+0x0b   /* Transmit Queue Counter */
30 #define EWRK3_TDQ    iobase+0x0c   /* Transmit Done Queue */
31 #define EWRK3_TDQC   iobase+0x0d   /* Transmit Done Queue Counter */
32 #define EWRK3_PIR1   iobase+0x0e   /* Page Index Register 1 */
33 #define EWRK3_PIR2   iobase+0x0f   /* Page Index Register 2 */
34 #define EWRK3_DATA   iobase+0x10   /* Data Register */
35 #define EWRK3_IOPR   iobase+0x11   /* I/O Page Register */
36 #define EWRK3_IOBR   iobase+0x12   /* I/O Base Register */
37 #define EWRK3_MPR    iobase+0x13   /* Memory Page Register */
38 #define EWRK3_MBR    iobase+0x14   /* Memory Base Register */
39 #define EWRK3_APROM  iobase+0x15   /* Address PROM */
40 #define EWRK3_EPROM1 iobase+0x16   /* EEPROM Data Register 1 */
41 #define EWRK3_EPROM2 iobase+0x17   /* EEPROM Data Register 2 */
42 #define EWRK3_PAR0   iobase+0x18   /* Physical Address Register 0 */
43 #define EWRK3_PAR1   iobase+0x19   /* Physical Address Register 1 */
44 #define EWRK3_PAR2   iobase+0x1a   /* Physical Address Register 2 */
45 #define EWRK3_PAR3   iobase+0x1b   /* Physical Address Register 3 */
46 #define EWRK3_PAR4   iobase+0x1c   /* Physical Address Register 4 */
47 #define EWRK3_PAR5   iobase+0x1d   /* Physical Address Register 5 */
48 #define EWRK3_CMR    iobase+0x1e   /* Configuration/Management Register */
175 #define EISA_ID       iobase + 0x0c80  /* EISA ID Registers */ 
176 #define EISA_ID0      iobase + 0x0c80  /* EISA ID Register 0 */ 
177 #define EISA_ID1      iobase + 0x0c81  /* EISA ID Register 1 */ 
178 #define EISA_ID2      iobase + 0x0c82  /* EISA ID Register 2 */ 
179 #define EISA_ID3      iobase + 0x0c83  /* EISA ID Register 3 */ 
180 #define EISA_CR       iobase + 0x0c84  /* EISA Control Register */