Lines Matching refs:GG82563_REG

2649 #define GG82563_REG(page, reg)    \  macro
2655         GG82563_REG(0, 16) /* PHY Specific Control */
2657         GG82563_REG(0, 17) /* PHY Specific Status */
2659         GG82563_REG(0, 18) /* Interrupt Enable */
2661         GG82563_REG(0, 19) /* PHY Specific Status 2 */
2663         GG82563_REG(0, 21) /* Receive Error Counter */
2665         GG82563_REG(0, 22) /* Page Select */
2667         GG82563_REG(0, 26) /* PHY Specific Control 2 */
2669         GG82563_REG(0, 29) /* Alternate Page Select */
2671         GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
2674         GG82563_REG(2, 21) /* MAC Specific Control Register */
2676         GG82563_REG(2, 26) /* MAC Specific Control 2 */
2679         GG82563_REG(5, 26) /* DSP Distance */
2683         GG82563_REG(193, 16) /* Kumeran Mode Control */
2685         GG82563_REG(193, 17) /* Port Reset */
2687         GG82563_REG(193, 18) /* Revision ID */
2689         GG82563_REG(193, 19) /* Device ID */
2691         GG82563_REG(193, 20) /* Power Management Control */
2693         GG82563_REG(193, 25) /* Rate Adaptation Control */
2697         GG82563_REG(194, 16) /* FIFO's Control/Status */
2699         GG82563_REG(194, 17) /* Control */
2701         GG82563_REG(194, 18) /* Inband Control */
2703         GG82563_REG(194, 19) /* Diagnostic */
2705         GG82563_REG(194, 20) /* Acknowledge Timeouts */
2707         GG82563_REG(194, 21) /* Advertised Ability */
2709         GG82563_REG(194, 23) /* Link Partner Advertised Ability */
2711         GG82563_REG(194, 24) /* Advertised Next Page */
2713         GG82563_REG(194, 25) /* Link Partner Advertised Next page */
2715         GG82563_REG(194, 26) /* Misc. */