Lines Matching refs:db
339 struct dmfe_board_info *db; /* board information structure */ in dmfe_init_one() local
350 dev = alloc_etherdev(sizeof(*db)); in dmfe_init_one()
397 db = dev->priv; in dmfe_init_one()
400 …db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->… in dmfe_init_one()
401 …db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_pt… in dmfe_init_one()
403 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr; in dmfe_init_one()
404 db->first_tx_desc_dma = db->desc_pool_dma_ptr; in dmfe_init_one()
405 db->buf_pool_start = db->buf_pool_ptr; in dmfe_init_one()
406 db->buf_pool_dma_start = db->buf_pool_dma_ptr; in dmfe_init_one()
408 db->chip_id = ent->driver_data; in dmfe_init_one()
409 db->ioaddr = pci_resource_start(pdev, 0); in dmfe_init_one()
410 db->chip_revision = dev_rev; in dmfe_init_one()
412 db->pdev = pdev; in dmfe_init_one()
414 dev->base_addr = db->ioaddr; in dmfe_init_one()
423 spin_lock_init(&db->lock); in dmfe_init_one()
428 db->chip_type = 1; /* DM9102A E3 */ in dmfe_init_one()
430 db->chip_type = 0; in dmfe_init_one()
434 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i)); in dmfe_init_one()
438 dev->dev_addr[i] = db->srom[20 + i]; in dmfe_init_one()
471 struct dmfe_board_info *db = dev->priv; in dmfe_remove_one() local
476 pci_free_consistent(db->pdev, sizeof(struct tx_desc) * in dmfe_remove_one()
477 DESC_ALL_CNT + 0x20, db->desc_pool_ptr, in dmfe_remove_one()
478 db->desc_pool_dma_ptr); in dmfe_remove_one()
479 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, in dmfe_remove_one()
480 db->buf_pool_ptr, db->buf_pool_dma_ptr); in dmfe_remove_one()
499 struct dmfe_board_info *db = dev->priv; in dmfe_open() local
508 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set; in dmfe_open()
509 db->tx_packet_cnt = 0; in dmfe_open()
510 db->tx_queue_cnt = 0; in dmfe_open()
511 db->rx_avail_cnt = 0; in dmfe_open()
512 db->link_failed = 1; in dmfe_open()
513 db->wait_reset = 0; in dmfe_open()
515 db->first_in_callback = 0; in dmfe_open()
516 db->NIC_capability = 0xf; /* All capability*/ in dmfe_open()
517 db->PHY_reg4 = 0x1e0; in dmfe_open()
520 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) || in dmfe_open()
521 (db->chip_revision >= 0x02000030) ) { in dmfe_open()
522 db->cr6_data |= DMFE_TXTH_256; in dmfe_open()
523 db->cr0_data = CR0_DEFAULT; in dmfe_open()
524 db->dm910x_chk_mode=4; /* Enter the normal mode */ in dmfe_open()
526 db->cr6_data |= CR6_SFT; /* Store & Forward mode */ in dmfe_open()
527 db->cr0_data = 0; in dmfe_open()
528 db->dm910x_chk_mode = 1; /* Enter the check mode */ in dmfe_open()
538 init_timer(&db->timer); in dmfe_open()
539 db->timer.expires = DMFE_TIMER_WUT + HZ * 2; in dmfe_open()
540 db->timer.data = (unsigned long)dev; in dmfe_open()
541 db->timer.function = &dmfe_timer; in dmfe_open()
542 add_timer(&db->timer); in dmfe_open()
557 struct dmfe_board_info *db = dev->priv; in dmfe_init_dm910x() local
558 unsigned long ioaddr = db->ioaddr; in dmfe_init_dm910x()
565 outl(db->cr0_data, ioaddr + DCR0); in dmfe_init_dm910x()
569 db->phy_addr = 1; in dmfe_init_dm910x()
572 dmfe_parse_srom(db); in dmfe_init_dm910x()
573 db->media_mode = dmfe_media_mode; in dmfe_init_dm910x()
577 if (db->chip_id == PCI_DM9009_ID) { in dmfe_init_dm910x()
584 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */ in dmfe_init_dm910x()
585 dmfe_set_phyxcer(db); in dmfe_init_dm910x()
588 if ( !(db->media_mode & DMFE_AUTO) ) in dmfe_init_dm910x()
589 db->op_mode = db->media_mode; /* Force Mode */ in dmfe_init_dm910x()
592 dmfe_descriptor_init(db, ioaddr); in dmfe_init_dm910x()
595 update_cr6(db->cr6_data, ioaddr); in dmfe_init_dm910x()
598 if (db->chip_id == PCI_DM9132_ID) in dmfe_init_dm910x()
604 db->cr7_data = CR7_DEFAULT; in dmfe_init_dm910x()
605 outl(db->cr7_data, ioaddr + DCR7); in dmfe_init_dm910x()
608 outl(db->cr15_data, ioaddr + DCR15); in dmfe_init_dm910x()
611 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000; in dmfe_init_dm910x()
612 update_cr6(db->cr6_data, ioaddr); in dmfe_init_dm910x()
623 struct dmfe_board_info *db = dev->priv; in dmfe_start_xmit() local
639 spin_lock_irqsave(&db->lock, flags); in dmfe_start_xmit()
642 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) { in dmfe_start_xmit()
643 spin_unlock_irqrestore(&db->lock, flags); in dmfe_start_xmit()
644 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_queue_cnt); in dmfe_start_xmit()
652 txptr = db->tx_insert_ptr; in dmfe_start_xmit()
657 db->tx_insert_ptr = txptr->next_tx_desc; in dmfe_start_xmit()
660 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) { in dmfe_start_xmit()
662 db->tx_packet_cnt++; /* Ready to send */ in dmfe_start_xmit()
666 db->tx_queue_cnt++; /* queue TX packet */ in dmfe_start_xmit()
671 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT ) in dmfe_start_xmit()
678 spin_unlock_irqrestore(&db->lock, flags); in dmfe_start_xmit()
679 outl(db->cr7_data, dev->base_addr + DCR7); in dmfe_start_xmit()
692 struct dmfe_board_info *db = dev->priv; in dmfe_stop() local
701 del_timer_sync(&db->timer); in dmfe_stop()
706 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); in dmfe_stop()
712 dmfe_free_rxbuffer(db); in dmfe_stop()
717 db->tx_fifo_underrun, db->tx_excessive_collision, in dmfe_stop()
718 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier, in dmfe_stop()
719 db->tx_jabber_timeout, db->reset_count, db->reset_cr8, in dmfe_stop()
720 db->reset_fatal, db->reset_TXtimeout); in dmfe_stop()
735 struct dmfe_board_info *db = (struct dmfe_board_info *) dev->priv; in dmfe_interrupt() local
746 spin_lock_irqsave(&db->lock, flags); in dmfe_interrupt()
749 db->cr5_data = inl(ioaddr + DCR5); in dmfe_interrupt()
750 outl(db->cr5_data, ioaddr + DCR5); in dmfe_interrupt()
751 if ( !(db->cr5_data & 0xc1) ) { in dmfe_interrupt()
752 spin_unlock_irqrestore(&db->lock, flags); in dmfe_interrupt()
760 if (db->cr5_data & 0x2000) { in dmfe_interrupt()
762 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data); in dmfe_interrupt()
763 db->reset_fatal++; in dmfe_interrupt()
764 db->wait_reset = 1; /* Need to RESET */ in dmfe_interrupt()
765 spin_unlock_irqrestore(&db->lock, flags); in dmfe_interrupt()
770 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt ) in dmfe_interrupt()
771 dmfe_rx_packet(dev, db); in dmfe_interrupt()
774 if (db->rx_avail_cnt<RX_DESC_CNT) in dmfe_interrupt()
775 allocate_rx_buffer(db); in dmfe_interrupt()
778 if ( db->cr5_data & 0x01) in dmfe_interrupt()
779 dmfe_free_tx_pkt(dev, db); in dmfe_interrupt()
782 if (db->dm910x_chk_mode & 0x2) { in dmfe_interrupt()
783 db->dm910x_chk_mode = 0x4; in dmfe_interrupt()
784 db->cr6_data |= 0x100; in dmfe_interrupt()
785 update_cr6(db->cr6_data, db->ioaddr); in dmfe_interrupt()
789 outl(db->cr7_data, ioaddr + DCR7); in dmfe_interrupt()
791 spin_unlock_irqrestore(&db->lock, flags); in dmfe_interrupt()
799 static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db) in dmfe_free_tx_pkt() argument
805 txptr = db->tx_remove_ptr; in dmfe_free_tx_pkt()
806 while(db->tx_packet_cnt) { in dmfe_free_tx_pkt()
813 db->tx_packet_cnt--; in dmfe_free_tx_pkt()
814 db->stats.tx_packets++; in dmfe_free_tx_pkt()
819 db->stats.collisions += (tdes0 >> 3) & 0xf; in dmfe_free_tx_pkt()
820 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff; in dmfe_free_tx_pkt()
822 db->stats.tx_errors++; in dmfe_free_tx_pkt()
825 db->tx_fifo_underrun++; in dmfe_free_tx_pkt()
826 if ( !(db->cr6_data & CR6_SFT) ) { in dmfe_free_tx_pkt()
827 db->cr6_data = db->cr6_data | CR6_SFT; in dmfe_free_tx_pkt()
828 update_cr6(db->cr6_data, db->ioaddr); in dmfe_free_tx_pkt()
832 db->tx_excessive_collision++; in dmfe_free_tx_pkt()
834 db->tx_late_collision++; in dmfe_free_tx_pkt()
836 db->tx_no_carrier++; in dmfe_free_tx_pkt()
838 db->tx_loss_carrier++; in dmfe_free_tx_pkt()
840 db->tx_jabber_timeout++; in dmfe_free_tx_pkt()
848 db->tx_remove_ptr = txptr; in dmfe_free_tx_pkt()
851 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) { in dmfe_free_tx_pkt()
853 db->tx_packet_cnt++; /* Ready to send */ in dmfe_free_tx_pkt()
854 db->tx_queue_cnt--; in dmfe_free_tx_pkt()
860 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT ) in dmfe_free_tx_pkt()
883 static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db) in dmfe_rx_packet() argument
890 rxptr = db->rx_ready_ptr; in dmfe_rx_packet()
892 while(db->rx_avail_cnt) { in dmfe_rx_packet()
897 db->rx_avail_cnt--; in dmfe_rx_packet()
898 db->interval_rx_cnt++; in dmfe_rx_packet()
900 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE); in dmfe_rx_packet()
905 dmfe_reuse_skb(db, rxptr->rx_skb_ptr); in dmfe_rx_packet()
914 db->stats.rx_errors++; in dmfe_rx_packet()
916 db->stats.rx_fifo_errors++; in dmfe_rx_packet()
918 db->stats.rx_crc_errors++; in dmfe_rx_packet()
920 db->stats.rx_length_errors++; in dmfe_rx_packet()
924 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) { in dmfe_rx_packet()
928 if ( (db->dm910x_chk_mode & 1) && in dmfe_rx_packet()
932 dmfe_reuse_skb(db, rxptr->rx_skb_ptr); in dmfe_rx_packet()
933 db->dm910x_chk_mode = 3; in dmfe_rx_packet()
944 dmfe_reuse_skb(db, rxptr->rx_skb_ptr); in dmfe_rx_packet()
952 db->stats.rx_packets++; in dmfe_rx_packet()
953 db->stats.rx_bytes += rxlen; in dmfe_rx_packet()
958 dmfe_reuse_skb(db, rxptr->rx_skb_ptr); in dmfe_rx_packet()
965 db->rx_ready_ptr = rxptr; in dmfe_rx_packet()
975 struct dmfe_board_info *db = (struct dmfe_board_info *)dev->priv; in dmfe_get_stats() local
978 return &db->stats; in dmfe_get_stats()
988 struct dmfe_board_info *db = dev->priv; in dmfe_set_filter_mode() local
992 spin_lock_irqsave(&db->lock, flags); in dmfe_set_filter_mode()
996 db->cr6_data |= CR6_PM | CR6_PBF; in dmfe_set_filter_mode()
997 update_cr6(db->cr6_data, db->ioaddr); in dmfe_set_filter_mode()
998 spin_unlock_irqrestore(&db->lock, flags); in dmfe_set_filter_mode()
1004 db->cr6_data &= ~(CR6_PM | CR6_PBF); in dmfe_set_filter_mode()
1005 db->cr6_data |= CR6_PAM; in dmfe_set_filter_mode()
1006 spin_unlock_irqrestore(&db->lock, flags); in dmfe_set_filter_mode()
1011 if (db->chip_id == PCI_DM9132_ID) in dmfe_set_filter_mode()
1015 spin_unlock_irqrestore(&db->lock, flags); in dmfe_set_filter_mode()
1047 struct dmfe_board_info *db = (struct dmfe_board_info *) dev->priv; in dmfe_timer() local
1051 spin_lock_irqsave(&db->lock, flags); in dmfe_timer()
1054 if (db->first_in_callback == 0) { in dmfe_timer()
1055 db->first_in_callback = 1; in dmfe_timer()
1056 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) { in dmfe_timer()
1057 db->cr6_data &= ~0x40000; in dmfe_timer()
1058 update_cr6(db->cr6_data, db->ioaddr); in dmfe_timer()
1059 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id); in dmfe_timer()
1060 db->cr6_data |= 0x40000; in dmfe_timer()
1061 update_cr6(db->cr6_data, db->ioaddr); in dmfe_timer()
1062 db->timer.expires = DMFE_TIMER_WUT + HZ * 2; in dmfe_timer()
1063 add_timer(&db->timer); in dmfe_timer()
1064 spin_unlock_irqrestore(&db->lock, flags); in dmfe_timer()
1071 if ( (db->dm910x_chk_mode & 0x1) && in dmfe_timer()
1072 (db->stats.rx_packets > MAX_CHECK_PACKET) ) in dmfe_timer()
1073 db->dm910x_chk_mode = 0x4; in dmfe_timer()
1076 tmp_cr8 = inl(db->ioaddr + DCR8); in dmfe_timer()
1077 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) { in dmfe_timer()
1078 db->reset_cr8++; in dmfe_timer()
1079 db->wait_reset = 1; in dmfe_timer()
1081 db->interval_rx_cnt = 0; in dmfe_timer()
1084 if ( db->tx_packet_cnt && in dmfe_timer()
1090 db->reset_TXtimeout++; in dmfe_timer()
1091 db->wait_reset = 1; in dmfe_timer()
1097 if (db->wait_reset) { in dmfe_timer()
1098 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt); in dmfe_timer()
1099 db->reset_count++; in dmfe_timer()
1101 db->first_in_callback = 0; in dmfe_timer()
1102 db->timer.expires = DMFE_TIMER_WUT; in dmfe_timer()
1103 add_timer(&db->timer); in dmfe_timer()
1104 spin_unlock_irqrestore(&db->lock, flags); in dmfe_timer()
1109 if (db->chip_id == PCI_DM9132_ID) in dmfe_timer()
1110 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */ in dmfe_timer()
1112 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */ in dmfe_timer()
1114 if ( ((db->chip_id == PCI_DM9102_ID) && in dmfe_timer()
1115 (db->chip_revision == 0x02000030)) || in dmfe_timer()
1116 ((db->chip_id == PCI_DM9132_ID) && in dmfe_timer()
1117 (db->chip_revision == 0x02000010)) ) { in dmfe_timer()
1125 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) { in dmfe_timer()
1128 db->link_failed = 1; in dmfe_timer()
1132 if ( !(db->media_mode & 0x38) ) in dmfe_timer()
1133 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id); in dmfe_timer()
1136 if (db->media_mode & DMFE_AUTO) { in dmfe_timer()
1138 db->cr6_data|=0x00040000; /* bit18=1, MII */ in dmfe_timer()
1139 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */ in dmfe_timer()
1140 update_cr6(db->cr6_data, db->ioaddr); in dmfe_timer()
1143 if ((tmp_cr12 & 0x3) && db->link_failed) { in dmfe_timer()
1145 db->link_failed = 0; in dmfe_timer()
1148 if ( (db->media_mode & DMFE_AUTO) && in dmfe_timer()
1149 dmfe_sense_speed(db) ) in dmfe_timer()
1150 db->link_failed = 1; in dmfe_timer()
1151 dmfe_process_mode(db); in dmfe_timer()
1156 if (db->HPNA_command & 0xf00) { in dmfe_timer()
1157 db->HPNA_timer--; in dmfe_timer()
1158 if (!db->HPNA_timer) in dmfe_timer()
1159 dmfe_HPNA_remote_cmd_chk(db); in dmfe_timer()
1163 db->timer.expires = DMFE_TIMER_WUT; in dmfe_timer()
1164 add_timer(&db->timer); in dmfe_timer()
1165 spin_unlock_irqrestore(&db->lock, flags); in dmfe_timer()
1179 struct dmfe_board_info *db = dev->priv; in dmfe_dynamic_reset() local
1184 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */ in dmfe_dynamic_reset()
1185 update_cr6(db->cr6_data, dev->base_addr); in dmfe_dynamic_reset()
1193 dmfe_free_rxbuffer(db); in dmfe_dynamic_reset()
1196 db->tx_packet_cnt = 0; in dmfe_dynamic_reset()
1197 db->tx_queue_cnt = 0; in dmfe_dynamic_reset()
1198 db->rx_avail_cnt = 0; in dmfe_dynamic_reset()
1199 db->link_failed = 1; in dmfe_dynamic_reset()
1200 db->wait_reset = 0; in dmfe_dynamic_reset()
1214 static void dmfe_free_rxbuffer(struct dmfe_board_info * db) in dmfe_free_rxbuffer() argument
1219 while (db->rx_avail_cnt) { in dmfe_free_rxbuffer()
1220 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr); in dmfe_free_rxbuffer()
1221 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc; in dmfe_free_rxbuffer()
1222 db->rx_avail_cnt--; in dmfe_free_rxbuffer()
1231 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb) in dmfe_reuse_skb() argument
1233 struct rx_desc *rxptr = db->rx_insert_ptr; in dmfe_reuse_skb()
1237 …rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE)… in dmfe_reuse_skb()
1240 db->rx_avail_cnt++; in dmfe_reuse_skb()
1241 db->rx_insert_ptr = rxptr->next_rx_desc; in dmfe_reuse_skb()
1243 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt); in dmfe_reuse_skb()
1252 static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr) in dmfe_descriptor_init() argument
1264 db->tx_insert_ptr = db->first_tx_desc; in dmfe_descriptor_init()
1265 db->tx_remove_ptr = db->first_tx_desc; in dmfe_descriptor_init()
1266 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */ in dmfe_descriptor_init()
1269 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT; in dmfe_descriptor_init()
1270 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT; in dmfe_descriptor_init()
1271 db->rx_insert_ptr = db->first_rx_desc; in dmfe_descriptor_init()
1272 db->rx_ready_ptr = db->first_rx_desc; in dmfe_descriptor_init()
1273 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */ in dmfe_descriptor_init()
1276 tmp_buf = db->buf_pool_start; in dmfe_descriptor_init()
1277 tmp_buf_dma = db->buf_pool_dma_start; in dmfe_descriptor_init()
1278 tmp_tx_dma = db->first_tx_desc_dma; in dmfe_descriptor_init()
1279 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) { in dmfe_descriptor_init()
1290 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma); in dmfe_descriptor_init()
1291 tmp_tx->next_tx_desc = db->first_tx_desc; in dmfe_descriptor_init()
1294 tmp_rx_dma=db->first_rx_desc_dma; in dmfe_descriptor_init()
1295 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) { in dmfe_descriptor_init()
1302 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma); in dmfe_descriptor_init()
1303 tmp_rx->next_rx_desc = db->first_rx_desc; in dmfe_descriptor_init()
1306 allocate_rx_buffer(db); in dmfe_descriptor_init()
1377 struct dmfe_board_info *db = dev->priv; in send_filter_frame() local
1386 txptr = db->tx_insert_ptr; in send_filter_frame()
1415 db->tx_insert_ptr = txptr->next_tx_desc; in send_filter_frame()
1419 if (!db->tx_packet_cnt) { in send_filter_frame()
1421 db->tx_packet_cnt++; in send_filter_frame()
1423 update_cr6(db->cr6_data | 0x2000, dev->base_addr); in send_filter_frame()
1425 update_cr6(db->cr6_data, dev->base_addr); in send_filter_frame()
1428 db->tx_queue_cnt++; /* Put in TX queue */ in send_filter_frame()
1437 static void allocate_rx_buffer(struct dmfe_board_info *db) in allocate_rx_buffer() argument
1442 rxptr = db->rx_insert_ptr; in allocate_rx_buffer()
1444 while(db->rx_avail_cnt < RX_DESC_CNT) { in allocate_rx_buffer()
1448 …rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE)… in allocate_rx_buffer()
1452 db->rx_avail_cnt++; in allocate_rx_buffer()
1455 db->rx_insert_ptr = rxptr; in allocate_rx_buffer()
1502 static u8 dmfe_sense_speed(struct dmfe_board_info * db) in dmfe_sense_speed() argument
1508 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr); in dmfe_sense_speed()
1510 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); in dmfe_sense_speed()
1511 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id); in dmfe_sense_speed()
1514 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */ in dmfe_sense_speed()
1515 phy_mode = phy_read(db->ioaddr, db->phy_addr, 7, db->chip_id) & 0xf000; in dmfe_sense_speed()
1517 phy_mode = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0xf000; in dmfe_sense_speed()
1520 case 0x1000: db->op_mode = DMFE_10MHF; break; in dmfe_sense_speed()
1521 case 0x2000: db->op_mode = DMFE_10MFD; break; in dmfe_sense_speed()
1522 case 0x4000: db->op_mode = DMFE_100MHF; break; in dmfe_sense_speed()
1523 case 0x8000: db->op_mode = DMFE_100MFD; break; in dmfe_sense_speed()
1524 default: db->op_mode = DMFE_10MHF; in dmfe_sense_speed()
1529 db->op_mode = DMFE_10MHF; in dmfe_sense_speed()
1544 static void dmfe_set_phyxcer(struct dmfe_board_info *db) in dmfe_set_phyxcer() argument
1549 db->cr6_data &= ~0x40000; in dmfe_set_phyxcer()
1550 update_cr6(db->cr6_data, db->ioaddr); in dmfe_set_phyxcer()
1553 if (db->chip_id == PCI_DM9009_ID) { in dmfe_set_phyxcer()
1554 phy_reg = phy_read(db->ioaddr, db->phy_addr, 18, db->chip_id) & ~0x1000; in dmfe_set_phyxcer()
1555 phy_write(db->ioaddr, db->phy_addr, 18, phy_reg, db->chip_id); in dmfe_set_phyxcer()
1559 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0; in dmfe_set_phyxcer()
1561 if (db->media_mode & DMFE_AUTO) { in dmfe_set_phyxcer()
1563 phy_reg |= db->PHY_reg4; in dmfe_set_phyxcer()
1566 switch(db->media_mode) { in dmfe_set_phyxcer()
1572 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61; in dmfe_set_phyxcer()
1577 phy_reg|=db->PHY_reg4; in dmfe_set_phyxcer()
1578 db->media_mode|=DMFE_AUTO; in dmfe_set_phyxcer()
1580 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id); in dmfe_set_phyxcer()
1583 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) ) in dmfe_set_phyxcer()
1584 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id); in dmfe_set_phyxcer()
1585 if ( !db->chip_type ) in dmfe_set_phyxcer()
1586 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); in dmfe_set_phyxcer()
1597 static void dmfe_process_mode(struct dmfe_board_info *db) in dmfe_process_mode() argument
1602 if (db->op_mode & 0x4) in dmfe_process_mode()
1603 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */ in dmfe_process_mode()
1605 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */ in dmfe_process_mode()
1608 if (db->op_mode & 0x10) /* 1M HomePNA */ in dmfe_process_mode()
1609 db->cr6_data |= 0x40000;/* External MII select */ in dmfe_process_mode()
1611 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */ in dmfe_process_mode()
1613 update_cr6(db->cr6_data, db->ioaddr); in dmfe_process_mode()
1616 if ( !(db->media_mode & 0x18)) { in dmfe_process_mode()
1618 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id); in dmfe_process_mode()
1622 switch(db->op_mode) { in dmfe_process_mode()
1628 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id); in dmfe_process_mode()
1629 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) ) in dmfe_process_mode()
1631 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id); in dmfe_process_mode()
1773 static void dmfe_parse_srom(struct dmfe_board_info * db) in dmfe_parse_srom() argument
1775 char * srom = db->srom; in dmfe_parse_srom()
1781 db->cr15_data = CR15_DEFAULT; in dmfe_parse_srom()
1787 db->NIC_capability = le16_to_cpup(srom + 34); in dmfe_parse_srom()
1788 db->PHY_reg4 = 0; in dmfe_parse_srom()
1790 switch( db->NIC_capability & tmp_reg ) { in dmfe_parse_srom()
1791 case 0x1: db->PHY_reg4 |= 0x0020; break; in dmfe_parse_srom()
1792 case 0x2: db->PHY_reg4 |= 0x0040; break; in dmfe_parse_srom()
1793 case 0x4: db->PHY_reg4 |= 0x0080; break; in dmfe_parse_srom()
1794 case 0x8: db->PHY_reg4 |= 0x0100; break; in dmfe_parse_srom()
1811 db->cr15_data |= 0x40; in dmfe_parse_srom()
1815 db->cr15_data |= 0x400; in dmfe_parse_srom()
1819 db->cr15_data |= 0x9800; in dmfe_parse_srom()
1823 db->HPNA_command = 1; in dmfe_parse_srom()
1827 db->HPNA_command |= 0x8000; in dmfe_parse_srom()
1832 case 0: db->HPNA_command |= 0x0904; break; in dmfe_parse_srom()
1833 case 1: db->HPNA_command |= 0x0a00; break; in dmfe_parse_srom()
1834 case 2: db->HPNA_command |= 0x0506; break; in dmfe_parse_srom()
1835 case 3: db->HPNA_command |= 0x0602; break; in dmfe_parse_srom()
1839 case 0: db->HPNA_command |= 0x0004; break; in dmfe_parse_srom()
1840 case 1: db->HPNA_command |= 0x0000; break; in dmfe_parse_srom()
1841 case 2: db->HPNA_command |= 0x0006; break; in dmfe_parse_srom()
1842 case 3: db->HPNA_command |= 0x0002; break; in dmfe_parse_srom()
1846 db->HPNA_present = 0; in dmfe_parse_srom()
1847 update_cr6(db->cr6_data|0x40000, db->ioaddr); in dmfe_parse_srom()
1848 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id); in dmfe_parse_srom()
1851 db->HPNA_timer = 8; in dmfe_parse_srom()
1852 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) { in dmfe_parse_srom()
1854 db->HPNA_present = 1; in dmfe_parse_srom()
1855 dmfe_program_DM9801(db, tmp_reg); in dmfe_parse_srom()
1858 db->HPNA_present = 2; in dmfe_parse_srom()
1859 dmfe_program_DM9802(db); in dmfe_parse_srom()
1870 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev) in dmfe_program_DM9801() argument
1877 db->HPNA_command |= 0x1000; in dmfe_program_DM9801()
1878 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id); in dmfe_program_DM9801()
1880 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id); in dmfe_program_DM9801()
1883 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id); in dmfe_program_DM9801()
1885 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id); in dmfe_program_DM9801()
1891 db->HPNA_command |= 0x1000; in dmfe_program_DM9801()
1892 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id); in dmfe_program_DM9801()
1894 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id); in dmfe_program_DM9801()
1898 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id); in dmfe_program_DM9801()
1899 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id); in dmfe_program_DM9801()
1900 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id); in dmfe_program_DM9801()
1908 static void dmfe_program_DM9802(struct dmfe_board_info * db) in dmfe_program_DM9802() argument
1913 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id); in dmfe_program_DM9802()
1914 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id); in dmfe_program_DM9802()
1916 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id); in dmfe_program_DM9802()
1925 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db) in dmfe_HPNA_remote_cmd_chk() argument
1930 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60; in dmfe_HPNA_remote_cmd_chk()
1939 if ( phy_reg != (db->HPNA_command & 0x0f00) ) { in dmfe_HPNA_remote_cmd_chk()
1940 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id); in dmfe_HPNA_remote_cmd_chk()
1941 db->HPNA_timer=8; in dmfe_HPNA_remote_cmd_chk()
1943 db->HPNA_timer=600; /* Match, every 10 minutes, check */ in dmfe_HPNA_remote_cmd_chk()