Lines Matching refs:iobase
16 #define DE4X5_BMR iobase+(0x000 << lp->bus) /* Bus Mode Register */
17 #define DE4X5_TPD iobase+(0x008 << lp->bus) /* Transmit Poll Demand Reg */
18 #define DE4X5_RPD iobase+(0x010 << lp->bus) /* Receive Poll Demand Reg */
19 #define DE4X5_RRBA iobase+(0x018 << lp->bus) /* RX Ring Base Address Reg */
20 #define DE4X5_TRBA iobase+(0x020 << lp->bus) /* TX Ring Base Address Reg */
21 #define DE4X5_STS iobase+(0x028 << lp->bus) /* Status Register */
22 #define DE4X5_OMR iobase+(0x030 << lp->bus) /* Operation Mode Register */
23 #define DE4X5_IMR iobase+(0x038 << lp->bus) /* Interrupt Mask Register */
24 #define DE4X5_MFC iobase+(0x040 << lp->bus) /* Missed Frame Counter */
25 #define DE4X5_APROM iobase+(0x048 << lp->bus) /* Ethernet Address PROM */
26 #define DE4X5_BROM iobase+(0x048 << lp->bus) /* Boot ROM Register */
27 #define DE4X5_SROM iobase+(0x048 << lp->bus) /* Serial ROM Register */
28 #define DE4X5_MII iobase+(0x048 << lp->bus) /* MII Interface Register */
29 #define DE4X5_DDR iobase+(0x050 << lp->bus) /* Data Diagnostic Register */
30 #define DE4X5_FDR iobase+(0x058 << lp->bus) /* Full Duplex Register */
31 #define DE4X5_GPT iobase+(0x058 << lp->bus) /* General Purpose Timer Reg.*/
32 #define DE4X5_GEP iobase+(0x060 << lp->bus) /* General Purpose Register */
33 #define DE4X5_SISR iobase+(0x060 << lp->bus) /* SIA Status Register */
34 #define DE4X5_SICR iobase+(0x068 << lp->bus) /* SIA Connectivity Register */
35 #define DE4X5_STRR iobase+(0x070 << lp->bus) /* SIA TX/RX Register */
36 #define DE4X5_SIGR iobase+(0x078 << lp->bus) /* SIA General Register */
41 #define EISA_ID iobase+0x0c80 /* EISA ID Registers */
42 #define EISA_ID0 iobase+0x0c80 /* EISA ID Register 0 */
43 #define EISA_ID1 iobase+0x0c81 /* EISA ID Register 1 */
44 #define EISA_ID2 iobase+0x0c82 /* EISA ID Register 2 */
45 #define EISA_ID3 iobase+0x0c83 /* EISA ID Register 3 */
46 #define EISA_CR iobase+0x0c84 /* EISA Control Register */
47 #define EISA_REG0 iobase+0x0c88 /* EISA Configuration Register 0 */
48 #define EISA_REG1 iobase+0x0c89 /* EISA Configuration Register 1 */
49 #define EISA_REG2 iobase+0x0c8a /* EISA Configuration Register 2 */
50 #define EISA_REG3 iobase+0x0c8f /* EISA Configuration Register 3 */
51 #define EISA_APROM iobase+0x0c90 /* Ethernet Address PROM */
56 #define PCI_CFID iobase+0x0008 /* PCI Configuration ID Register */
57 #define PCI_CFCS iobase+0x000c /* PCI Command/Status Register */
58 #define PCI_CFRV iobase+0x0018 /* PCI Revision Register */
59 #define PCI_CFLT iobase+0x001c /* PCI Latency Timer Register */
60 #define PCI_CBIO iobase+0x0028 /* PCI Base I/O Register */
61 #define PCI_CBMA iobase+0x002c /* PCI Base Memory Address Register */
62 #define PCI_CBER iobase+0x0030 /* PCI Expansion ROM Base Address Reg. */
63 #define PCI_CFIT iobase+0x003c /* PCI Configuration Interrupt Register */
64 #define PCI_CFDA iobase+0x0040 /* PCI Driver Area Register */
65 #define PCI_CFDD iobase+0x0041 /* PCI Driver Dependent Area Register */
66 #define PCI_CFPM iobase+0x0043 /* PCI Power Management Area Register */