Lines Matching refs:cs
64 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val) in Write_hfc() argument
69 byteout(cs->hw.hfcsx.base+1, regnum); in Write_hfc()
70 byteout(cs->hw.hfcsx.base, val); in Write_hfc()
75 Read_hfc(struct IsdnCardState *cs, u_char regnum) in Read_hfc() argument
81 byteout(cs->hw.hfcsx.base+1, regnum); in Read_hfc()
82 ret = bytein(cs->hw.hfcsx.base); in Read_hfc()
92 fifo_select(struct IsdnCardState *cs, u_char fifo) in fifo_select() argument
95 if (fifo == cs->hw.hfcsx.last_fifo) in fifo_select()
100 byteout(cs->hw.hfcsx.base+1, HFCSX_FIF_SEL); in fifo_select()
101 byteout(cs->hw.hfcsx.base, fifo); in fifo_select()
102 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ in fifo_select()
104 byteout(cs->hw.hfcsx.base, fifo); in fifo_select()
105 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ in fifo_select()
114 reset_fifo(struct IsdnCardState *cs, u_char fifo) in reset_fifo() argument
119 fifo_select(cs, fifo); /* first select the fifo */ in reset_fifo()
120 byteout(cs->hw.hfcsx.base+1, HFCSX_CIRM); in reset_fifo()
121 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */ in reset_fifo()
123 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ in reset_fifo()
134 write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans_max) in write_fifo() argument
142 fifo_select(cs, fifo); in write_fifo()
149 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ in write_fifo()
153 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); in write_fifo()
154 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); in write_fifo()
158 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); in write_fifo()
159 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); in write_fifo()
169 Write_hfc(cs, HFCSX_FIF_DWR, *src++); in write_fifo()
173 msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker; in write_fifo()
175 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk; in write_fifo()
176 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk; in write_fifo()
182 if (cs->debug & L1_DEB_ISAC_FIFO) in write_fifo()
183 debugl1(cs, "hfcsx_write_fifo %d more as %d frames",fifo,f_msk-1); in write_fifo()
189 if (cs->debug & L1_DEB_ISAC_FIFO) in write_fifo()
190 debugl1(cs, "hfcsx_write_fifo %d f1(%x) f2(%x) z1(f1)(%x)", in write_fifo()
197 if (cs->debug & L1_DEB_ISAC_FIFO) in write_fifo()
198 debugl1(cs, "hfcsx_write_fifo %d count(%ld/%d)", in write_fifo()
201 if (cs->debug & L1_DEB_ISAC_FIFO) in write_fifo()
202 debugl1(cs, "hfcsx_write_fifo %d no fifo mem", fifo); in write_fifo()
209 Write_hfc(cs, HFCSX_FIF_DWR, *src++); in write_fifo()
211 Read_hfc(cs, HFCSX_FIF_INCF1); /* increment F1 */ in write_fifo()
213 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ in write_fifo()
223 read_fifo(struct IsdnCardState *cs, u_char fifo, int trans_max) in read_fifo() argument
229 fifo_select(cs, fifo); in read_fifo()
236 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ in read_fifo()
242 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); in read_fifo()
243 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); in read_fifo()
244 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); in read_fifo()
245 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); in read_fifo()
256 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD); in read_fifo()
263 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk; in read_fifo()
264 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk; in read_fifo()
268 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); in read_fifo()
269 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); in read_fifo()
270 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); in read_fifo()
271 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); in read_fifo()
273 if (cs->debug & L1_DEB_ISAC_FIFO) in read_fifo()
274 debugl1(cs, "hfcsx_read_fifo %d f1(%x) f2(%x) z1(f2)(%x) z2(f2)(%x)", in read_fifo()
282 if (cs->debug & L1_DEB_ISAC_FIFO) in read_fifo()
283 debugl1(cs, "hfcsx_read_fifo %d count %ld)", in read_fifo()
287 if (cs->debug & L1_DEB_WARN) in read_fifo()
288 debugl1(cs, "hfcsx_read_fifo %d paket inv. len %d ", fifo , count); in read_fifo()
291 Read_hfc(cs, HFCSX_FIF_DRD); in read_fifo()
300 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD); in read_fifo()
302 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 1 */ in read_fifo()
303 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 2 */ in read_fifo()
304 if (Read_hfc(cs, HFCSX_FIF_DRD)) { in read_fifo()
306 if (cs->debug & L1_DEB_ISAC_FIFO) in read_fifo()
307 debugl1(cs, "hfcsx_read_fifo %d crc error", fifo); in read_fifo()
315 Read_hfc(cs, HFCSX_FIF_INCF2); /* increment F2 */ in read_fifo()
317 while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */ in read_fifo()
327 release_io_hfcsx(struct IsdnCardState *cs) in release_io_hfcsx() argument
333 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ in release_io_hfcsx()
334 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in release_io_hfcsx()
336 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET); /* Reset On */ in release_io_hfcsx()
340 Write_hfc(cs, HFCSX_CIRM, 0); /* Reset Off */ in release_io_hfcsx()
341 del_timer(&cs->hw.hfcsx.timer); in release_io_hfcsx()
342 release_region(cs->hw.hfcsx.base, 2); /* release IO-Block */ in release_io_hfcsx()
343 kfree(cs->hw.hfcsx.extra); in release_io_hfcsx()
344 cs->hw.hfcsx.extra = NULL; in release_io_hfcsx()
351 static int set_fifo_size(struct IsdnCardState *cs) in set_fifo_size() argument
354 if (cs->hw.hfcsx.b_fifo_size) return(1); /* already determined */ in set_fifo_size()
356 if ((cs->hw.hfcsx.chip >> 4) == 9) { in set_fifo_size()
357 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K; in set_fifo_size()
361 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K; in set_fifo_size()
362 cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */ in set_fifo_size()
372 reset_hfcsx(struct IsdnCardState *cs) in reset_hfcsx() argument
378 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ in reset_hfcsx()
379 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in reset_hfcsx()
383 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm ); /* Reset */ in reset_hfcsx()
387 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */ in reset_hfcsx()
390 if (Read_hfc(cs, HFCSX_STATUS) & 2) in reset_hfcsx()
392 cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */ in reset_hfcsx()
393 if (!set_fifo_size(cs)) continue; in reset_hfcsx()
397 cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK; /* no echo connect , threshold */ in reset_hfcsx()
398 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in reset_hfcsx()
400 Write_hfc(cs, HFCSX_CLKDEL, 0x0e); /* ST-Bit delay for TE-Mode */ in reset_hfcsx()
401 cs->hw.hfcsx.sctrl_e = HFCSX_AUTO_AWAKE; in reset_hfcsx()
402 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); /* S/T Auto awake */ in reset_hfcsx()
403 cs->hw.hfcsx.bswapped = 0; /* no exchange */ in reset_hfcsx()
404 cs->hw.hfcsx.nt_mode = 0; /* we are in TE mode */ in reset_hfcsx()
405 cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER; in reset_hfcsx()
406 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in reset_hfcsx()
408 cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC | in reset_hfcsx()
410 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in reset_hfcsx()
413 if (Read_hfc(cs, HFCSX_INT_S1)); in reset_hfcsx()
415 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 2); /* HFC ST 2 */ in reset_hfcsx()
417 Write_hfc(cs, HFCSX_STATES, 2); /* HFC ST 2 */ in reset_hfcsx()
418 cs->hw.hfcsx.mst_m = HFCSX_MASTER; /* HFC Master Mode */ in reset_hfcsx()
420 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in reset_hfcsx()
421 cs->hw.hfcsx.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */ in reset_hfcsx()
422 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in reset_hfcsx()
423 cs->hw.hfcsx.sctrl_r = 0; in reset_hfcsx()
424 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in reset_hfcsx()
433 cs->hw.hfcsx.conn = 0x36; /* set data flow directions */ in reset_hfcsx()
434 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in reset_hfcsx()
435 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */ in reset_hfcsx()
436 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */ in reset_hfcsx()
437 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */ in reset_hfcsx()
438 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */ in reset_hfcsx()
441 cs->hw.hfcsx.int_m2 = HFCSX_IRQ_ENABLE; in reset_hfcsx()
442 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in reset_hfcsx()
443 if (Read_hfc(cs, HFCSX_INT_S2)); in reset_hfcsx()
451 hfcsx_Timer(struct IsdnCardState *cs) in hfcsx_Timer() argument
453 cs->hw.hfcsx.timer.expires = jiffies + 75; in hfcsx_Timer()
465 sched_event_D_sx(struct IsdnCardState *cs, int event) in sched_event_D_sx() argument
467 test_and_set_bit(event, &cs->event); in sched_event_D_sx()
468 queue_task(&cs->tqueue, &tq_immediate); in sched_event_D_sx()
488 Sel_BCS(struct IsdnCardState *cs, int channel) in Sel_BCS() argument
490 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel)) in Sel_BCS()
491 return (&cs->bcs[0]); in Sel_BCS()
492 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel)) in Sel_BCS()
493 return (&cs->bcs[1]); in Sel_BCS()
503 receive_dmsg(struct IsdnCardState *cs) in receive_dmsg() argument
508 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in receive_dmsg()
509 debugl1(cs, "rec_dmsg blocked"); in receive_dmsg()
514 skb = read_fifo(cs, HFCSX_SEL_D_RX, 0); in receive_dmsg()
516 skb_queue_tail(&cs->rq, skb); in receive_dmsg()
517 sched_event_D_sx(cs, D_RCVBUFREADY); in receive_dmsg()
521 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in receive_dmsg()
532 struct IsdnCardState *cs = bcs->cs; in main_rec_hfcsx() local
541 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in main_rec_hfcsx()
542 debugl1(cs, "rec_data %d blocked", bcs->channel); in main_rec_hfcsx()
547 skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? in main_rec_hfcsx()
559 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in main_rec_hfcsx()
570 hfcsx_fill_dfifo(struct IsdnCardState *cs) in hfcsx_fill_dfifo() argument
572 if (!cs->tx_skb) in hfcsx_fill_dfifo()
574 if (cs->tx_skb->len <= 0) in hfcsx_fill_dfifo()
577 if (write_fifo(cs, cs->tx_skb, HFCSX_SEL_D_TX, 0)) { in hfcsx_fill_dfifo()
578 dev_kfree_skb_any(cs->tx_skb); in hfcsx_fill_dfifo()
579 cs->tx_skb = NULL; in hfcsx_fill_dfifo()
590 struct IsdnCardState *cs = bcs->cs; in hfcsx_fill_fifo() local
601 if (write_fifo(cs, bcs->tx_skb, in hfcsx_fill_fifo()
602 ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? in hfcsx_fill_fifo()
627 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; in dch_nt_l2l1() local
640 debugl1(cs, "PH_TEST_LOOP B1"); in dch_nt_l2l1()
642 debugl1(cs, "PH_TEST_LOOP B2"); in dch_nt_l2l1()
644 debugl1(cs, "PH_TEST_LOOP DISABLED"); in dch_nt_l2l1()
648 if (cs->debug) in dch_nt_l2l1()
649 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr); in dch_nt_l2l1()
660 hfcsx_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic) in hfcsx_auxcmd() argument
666 …(!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_… in hfcsx_auxcmd()
669 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0); /* HFC ST G0 */ in hfcsx_auxcmd()
671 cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT; in hfcsx_auxcmd()
672 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */ in hfcsx_auxcmd()
674 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 1); /* HFC ST G1 */ in hfcsx_auxcmd()
676 Write_hfc(cs, HFCSX_STATES, 1 | HFCSX_ACTIVATE | HFCSX_DO_ACTION); in hfcsx_auxcmd()
677 cs->dc.hfcsx.ph_state = 1; in hfcsx_auxcmd()
678 cs->hw.hfcsx.nt_mode = 1; in hfcsx_auxcmd()
679 cs->hw.hfcsx.nt_timer = 0; in hfcsx_auxcmd()
680 cs->stlist->l2.l2l1 = dch_nt_l2l1; in hfcsx_auxcmd()
682 debugl1(cs, "NT mode activated"); in hfcsx_auxcmd()
685 if ((cs->chanlimit > 1) || (cs->hw.hfcsx.bswapped) || in hfcsx_auxcmd()
686 (cs->hw.hfcsx.nt_mode) || (ic->arg != 12)) in hfcsx_auxcmd()
692 cs->logecho = 1; in hfcsx_auxcmd()
693 cs->hw.hfcsx.trm |= 0x20; /* enable echo chan */ in hfcsx_auxcmd()
694 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_B2REC; in hfcsx_auxcmd()
697 cs->logecho = 0; in hfcsx_auxcmd()
698 cs->hw.hfcsx.trm &= ~0x20; /* disable echo chan */ in hfcsx_auxcmd()
699 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_B2REC; in hfcsx_auxcmd()
701 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; in hfcsx_auxcmd()
702 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; in hfcsx_auxcmd()
703 cs->hw.hfcsx.conn |= 0x10; /* B2-IOM -> B2-ST */ in hfcsx_auxcmd()
704 cs->hw.hfcsx.ctmt &= ~2; in hfcsx_auxcmd()
705 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in hfcsx_auxcmd()
706 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in hfcsx_auxcmd()
707 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in hfcsx_auxcmd()
708 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in hfcsx_auxcmd()
709 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in hfcsx_auxcmd()
710 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_auxcmd()
719 receive_emsg(struct IsdnCardState *cs) in receive_emsg() argument
729 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in receive_emsg()
730 debugl1(cs, "echo_rec_data blocked"); in receive_emsg()
737 skb = read_fifo(cs, HFCSX_SEL_B2_RX, 0); in receive_emsg()
739 if (cs->debug & DEB_DLOG_HEX) { in receive_emsg()
740 ptr = cs->dlog; in receive_emsg()
751 HiSax_putstatus(cs, NULL, cs->dlog); in receive_emsg()
753 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len); in receive_emsg()
759 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in receive_emsg()
771 struct IsdnCardState *cs = dev_id; in hfcsx_interrupt() local
778 if (!cs) { in hfcsx_interrupt()
782 if (!(cs->hw.hfcsx.int_m2 & 0x08)) in hfcsx_interrupt()
785 if (HFCSX_ANYINT & (stat = Read_hfc(cs, HFCSX_STATUS))) { in hfcsx_interrupt()
786 val = Read_hfc(cs, HFCSX_INT_S1); in hfcsx_interrupt()
787 if (cs->debug & L1_DEB_ISAC) in hfcsx_interrupt()
788 debugl1(cs, "HFC-SX: stat(%02x) s1(%02x)", stat, val); in hfcsx_interrupt()
792 if (cs->debug & L1_DEB_ISAC) in hfcsx_interrupt()
793 debugl1(cs, "HFC-SX irq %x %s", val, in hfcsx_interrupt()
794 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ? in hfcsx_interrupt()
796 val &= cs->hw.hfcsx.int_m1; in hfcsx_interrupt()
798 exval = Read_hfc(cs, HFCSX_STATES) & 0xf; in hfcsx_interrupt()
799 if (cs->debug & L1_DEB_ISAC) in hfcsx_interrupt()
800 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcsx.ph_state, in hfcsx_interrupt()
802 cs->dc.hfcsx.ph_state = exval; in hfcsx_interrupt()
803 sched_event_D_sx(cs, D_L1STATECHANGE); in hfcsx_interrupt()
807 if (cs->hw.hfcsx.nt_mode) { in hfcsx_interrupt()
808 if ((--cs->hw.hfcsx.nt_timer) < 0) in hfcsx_interrupt()
809 sched_event_D_sx(cs, D_L1STATECHANGE); in hfcsx_interrupt()
812 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_interrupt()
817 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
818 cs->hw.hfcsx.int_s1 |= val; in hfcsx_interrupt()
822 if (cs->hw.hfcsx.int_s1 & 0x18) { in hfcsx_interrupt()
824 val = cs->hw.hfcsx.int_s1; in hfcsx_interrupt()
825 cs->hw.hfcsx.int_s1 = exval; in hfcsx_interrupt()
828 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { in hfcsx_interrupt()
829 if (cs->debug) in hfcsx_interrupt()
830 debugl1(cs, "hfcsx spurious 0x08 IRQ"); in hfcsx_interrupt()
835 if (cs->logecho) in hfcsx_interrupt()
836 receive_emsg(cs); in hfcsx_interrupt()
837 else if (!(bcs = Sel_BCS(cs, 1))) { in hfcsx_interrupt()
838 if (cs->debug) in hfcsx_interrupt()
839 debugl1(cs, "hfcsx spurious 0x10 IRQ"); in hfcsx_interrupt()
844 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { in hfcsx_interrupt()
845 if (cs->debug) in hfcsx_interrupt()
846 debugl1(cs, "hfcsx spurious 0x01 IRQ"); in hfcsx_interrupt()
849 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
851 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
853 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcsx_interrupt()
856 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
858 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
860 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcsx_interrupt()
868 if (!(bcs = Sel_BCS(cs, 1))) { in hfcsx_interrupt()
869 if (cs->debug) in hfcsx_interrupt()
870 debugl1(cs, "hfcsx spurious 0x02 IRQ"); in hfcsx_interrupt()
873 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
875 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
877 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcsx_interrupt()
880 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
882 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
884 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcsx_interrupt()
892 receive_dmsg(cs); in hfcsx_interrupt()
895 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) in hfcsx_interrupt()
896 del_timer(&cs->dbusytimer); in hfcsx_interrupt()
897 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) in hfcsx_interrupt()
898 sched_event_D_sx(cs, D_CLEARBUSY); in hfcsx_interrupt()
899 if (cs->tx_skb) { in hfcsx_interrupt()
900 if (cs->tx_skb->len) { in hfcsx_interrupt()
901 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
902 hfcsx_fill_dfifo(cs); in hfcsx_interrupt()
903 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
905 debugl1(cs, "hfcsx_fill_dfifo irq blocked"); in hfcsx_interrupt()
909 dev_kfree_skb_irq(cs->tx_skb); in hfcsx_interrupt()
910 cs->tx_cnt = 0; in hfcsx_interrupt()
911 cs->tx_skb = NULL; in hfcsx_interrupt()
914 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { in hfcsx_interrupt()
915 cs->tx_cnt = 0; in hfcsx_interrupt()
916 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
917 hfcsx_fill_dfifo(cs); in hfcsx_interrupt()
918 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
920 debugl1(cs, "hfcsx_fill_dfifo irq blocked"); in hfcsx_interrupt()
923 sched_event_D_sx(cs, D_XMTBUFREADY); in hfcsx_interrupt()
926 if (cs->hw.hfcsx.int_s1 && count--) { in hfcsx_interrupt()
927 val = cs->hw.hfcsx.int_s1; in hfcsx_interrupt()
928 cs->hw.hfcsx.int_s1 = 0; in hfcsx_interrupt()
929 if (cs->debug & L1_DEB_ISAC) in hfcsx_interrupt()
930 debugl1(cs, "HFC-SX irq %x loop %d", val, 15 - count); in hfcsx_interrupt()
941 hfcsx_dbusy_timer(struct IsdnCardState *cs) in hfcsx_dbusy_timer() argument
951 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; in HFCSX_l1hw() local
957 if (cs->debug & DEB_DLOG_HEX) in HFCSX_l1hw()
958 LogFrame(cs, skb->data, skb->len); in HFCSX_l1hw()
959 if (cs->debug & DEB_DLOG_VERBOSE) in HFCSX_l1hw()
960 dlogframe(cs, skb, 0); in HFCSX_l1hw()
961 if (cs->tx_skb) { in HFCSX_l1hw()
962 skb_queue_tail(&cs->sq, skb); in HFCSX_l1hw()
964 if (cs->debug & L1_DEB_LAPD) in HFCSX_l1hw()
965 Logl2Frame(cs, skb, "PH_DATA Queued", 0); in HFCSX_l1hw()
968 cs->tx_skb = skb; in HFCSX_l1hw()
969 cs->tx_cnt = 0; in HFCSX_l1hw()
971 if (cs->debug & L1_DEB_LAPD) in HFCSX_l1hw()
972 Logl2Frame(cs, skb, "PH_DATA", 0); in HFCSX_l1hw()
974 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in HFCSX_l1hw()
975 hfcsx_fill_dfifo(cs); in HFCSX_l1hw()
976 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in HFCSX_l1hw()
978 debugl1(cs, "hfcsx_fill_dfifo blocked"); in HFCSX_l1hw()
983 if (cs->tx_skb) { in HFCSX_l1hw()
984 if (cs->debug & L1_DEB_WARN) in HFCSX_l1hw()
985 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); in HFCSX_l1hw()
986 skb_queue_tail(&cs->sq, skb); in HFCSX_l1hw()
989 if (cs->debug & DEB_DLOG_HEX) in HFCSX_l1hw()
990 LogFrame(cs, skb->data, skb->len); in HFCSX_l1hw()
991 if (cs->debug & DEB_DLOG_VERBOSE) in HFCSX_l1hw()
992 dlogframe(cs, skb, 0); in HFCSX_l1hw()
993 cs->tx_skb = skb; in HFCSX_l1hw()
994 cs->tx_cnt = 0; in HFCSX_l1hw()
996 if (cs->debug & L1_DEB_LAPD) in HFCSX_l1hw()
997 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); in HFCSX_l1hw()
999 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in HFCSX_l1hw()
1000 hfcsx_fill_dfifo(cs); in HFCSX_l1hw()
1001 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in HFCSX_l1hw()
1003 debugl1(cs, "hfcsx_fill_dfifo blocked"); in HFCSX_l1hw()
1007 if (cs->debug & L1_DEB_LAPD) in HFCSX_l1hw()
1008 debugl1(cs, "-> PH_REQUEST_PULL"); in HFCSX_l1hw()
1010 if (!cs->tx_skb) { in HFCSX_l1hw()
1017 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3); /* HFC ST 3 */ in HFCSX_l1hw()
1019 Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */ in HFCSX_l1hw()
1020 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; in HFCSX_l1hw()
1021 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
1022 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); in HFCSX_l1hw()
1023 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); in HFCSX_l1hw()
1026 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); in HFCSX_l1hw()
1029 cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER; in HFCSX_l1hw()
1030 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
1033 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; in HFCSX_l1hw()
1034 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
1039 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* tx slot */ in HFCSX_l1hw()
1040 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* rx slot */ in HFCSX_l1hw()
1043 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1; in HFCSX_l1hw()
1044 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in HFCSX_l1hw()
1049 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* tx slot */ in HFCSX_l1hw()
1050 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* rx slot */ in HFCSX_l1hw()
1053 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08; in HFCSX_l1hw()
1054 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in HFCSX_l1hw()
1059 if (cs->debug & L1_DEB_WARN) in HFCSX_l1hw()
1060 debugl1(cs, "hfcsx_l1hw loop invalid %4x", (int) arg); in HFCSX_l1hw()
1065 cs->hw.hfcsx.trm |= 0x80; /* enable IOM-loop */ in HFCSX_l1hw()
1066 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in HFCSX_l1hw()
1070 if (cs->debug & L1_DEB_WARN) in HFCSX_l1hw()
1071 debugl1(cs, "hfcsx_l1hw unknown pr %4x", pr); in HFCSX_l1hw()
1080 setstack_hfcsx(struct PStack *st, struct IsdnCardState *cs) in setstack_hfcsx() argument
1091 struct IsdnCardState *cs = bcs->cs; in hfcsx_send_data() local
1093 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_send_data()
1095 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_send_data()
1097 debugl1(cs, "send_data %d blocked", bcs->channel); in hfcsx_send_data()
1106 struct IsdnCardState *cs = bcs->cs; in mode_hfcsx() local
1110 if (cs->debug & L1_DEB_HSCX) in mode_hfcsx()
1111 debugl1(cs, "HFCSX bchannel mode %d bchan %d/%d", in mode_hfcsx()
1118 if (cs->chanlimit > 1) { in mode_hfcsx()
1119 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcsx()
1120 cs->hw.hfcsx.sctrl_e &= ~0x80; in mode_hfcsx()
1124 cs->hw.hfcsx.bswapped = 1; /* B1 and B2 exchanged */ in mode_hfcsx()
1125 cs->hw.hfcsx.sctrl_e |= 0x80; in mode_hfcsx()
1127 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcsx()
1128 cs->hw.hfcsx.sctrl_e &= ~0x80; in mode_hfcsx()
1132 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcsx()
1133 cs->hw.hfcsx.sctrl_e &= ~0x80; in mode_hfcsx()
1139 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; in mode_hfcsx()
1140 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; in mode_hfcsx()
1142 cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA; in mode_hfcsx()
1143 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA; in mode_hfcsx()
1146 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1148 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1153 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; in mode_hfcsx()
1154 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; in mode_hfcsx()
1156 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; in mode_hfcsx()
1157 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; in mode_hfcsx()
1160 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1161 cs->hw.hfcsx.ctmt |= 2; in mode_hfcsx()
1162 cs->hw.hfcsx.conn &= ~0x18; in mode_hfcsx()
1164 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1165 cs->hw.hfcsx.ctmt |= 1; in mode_hfcsx()
1166 cs->hw.hfcsx.conn &= ~0x03; in mode_hfcsx()
1171 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; in mode_hfcsx()
1172 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; in mode_hfcsx()
1174 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; in mode_hfcsx()
1175 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; in mode_hfcsx()
1178 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1179 cs->hw.hfcsx.ctmt &= ~2; in mode_hfcsx()
1180 cs->hw.hfcsx.conn &= ~0x18; in mode_hfcsx()
1182 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1183 cs->hw.hfcsx.ctmt &= ~1; in mode_hfcsx()
1184 cs->hw.hfcsx.conn &= ~0x03; in mode_hfcsx()
1189 cs->hw.hfcsx.conn |= 0x10; in mode_hfcsx()
1190 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; in mode_hfcsx()
1191 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; in mode_hfcsx()
1192 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1194 cs->hw.hfcsx.conn |= 0x02; in mode_hfcsx()
1195 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; in mode_hfcsx()
1196 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; in mode_hfcsx()
1197 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1201 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); in mode_hfcsx()
1202 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in mode_hfcsx()
1203 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in mode_hfcsx()
1204 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in mode_hfcsx()
1205 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in mode_hfcsx()
1206 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in mode_hfcsx()
1208 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX); in mode_hfcsx()
1209 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX); in mode_hfcsx()
1233 */ st->l1.bcs->cs->BC_Send_Data(st->l1.bcs); in hfcsx_l2l1()
1246 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs); in hfcsx_l2l1()
1295 open_hfcsxstate(struct IsdnCardState *cs, struct BCState *bcs) in open_hfcsxstate() argument
1329 hfcsx_bh(struct IsdnCardState *cs) in hfcsx_bh() argument
1334 if (!cs) in hfcsx_bh()
1336 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) { in hfcsx_bh()
1337 if (!cs->hw.hfcsx.nt_mode) in hfcsx_bh()
1338 switch (cs->dc.hfcsx.ph_state) { in hfcsx_bh()
1340 l1_msg(cs, HW_RESET | INDICATION, NULL); in hfcsx_bh()
1343 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); in hfcsx_bh()
1346 l1_msg(cs, HW_RSYNC | INDICATION, NULL); in hfcsx_bh()
1349 l1_msg(cs, HW_INFO2 | INDICATION, NULL); in hfcsx_bh()
1352 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); in hfcsx_bh()
1357 switch (cs->dc.hfcsx.ph_state) { in hfcsx_bh()
1361 if (cs->hw.hfcsx.nt_timer < 0) { in hfcsx_bh()
1362 cs->hw.hfcsx.nt_timer = 0; in hfcsx_bh()
1363 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; in hfcsx_bh()
1364 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1366 if (Read_hfc(cs, HFCSX_INT_S1)); in hfcsx_bh()
1368 Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE); in hfcsx_bh()
1370 Write_hfc(cs, HFCSX_STATES, 4); in hfcsx_bh()
1371 cs->dc.hfcsx.ph_state = 4; in hfcsx_bh()
1373 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER; in hfcsx_bh()
1374 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1375 cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER; in hfcsx_bh()
1376 cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125; in hfcsx_bh()
1377 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_bh()
1378 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_bh()
1379 cs->hw.hfcsx.nt_timer = NT_T1_COUNT; in hfcsx_bh()
1380 Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3); /* allow G2 -> G3 transition */ in hfcsx_bh()
1389 cs->hw.hfcsx.nt_timer = 0; in hfcsx_bh()
1390 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; in hfcsx_bh()
1391 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1399 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) in hfcsx_bh()
1400 DChannel_proc_rcv(cs); in hfcsx_bh()
1401 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) in hfcsx_bh()
1402 DChannel_proc_xmt(cs); in hfcsx_bh()
1410 inithfcsx(struct IsdnCardState *cs) in inithfcsx() argument
1412 cs->setstack_d = setstack_hfcsx; in inithfcsx()
1413 cs->dbusytimer.function = (void *) hfcsx_dbusy_timer; in inithfcsx()
1414 cs->dbusytimer.data = (long) cs; in inithfcsx()
1415 init_timer(&cs->dbusytimer); in inithfcsx()
1416 cs->tqueue.routine = (void *) (void *) hfcsx_bh; in inithfcsx()
1417 cs->BC_Send_Data = &hfcsx_send_data; in inithfcsx()
1418 cs->bcs[0].BC_SetStack = setstack_2b; in inithfcsx()
1419 cs->bcs[1].BC_SetStack = setstack_2b; in inithfcsx()
1420 cs->bcs[0].BC_Close = close_hfcsx; in inithfcsx()
1421 cs->bcs[1].BC_Close = close_hfcsx; in inithfcsx()
1422 mode_hfcsx(cs->bcs, 0, 0); in inithfcsx()
1423 mode_hfcsx(cs->bcs + 1, 0, 1); in inithfcsx()
1432 hfcsx_card_msg(struct IsdnCardState *cs, int mt, void *arg) in hfcsx_card_msg() argument
1436 if (cs->debug & L1_DEB_ISAC) in hfcsx_card_msg()
1437 debugl1(cs, "HFCSX: card_msg %x", mt); in hfcsx_card_msg()
1440 reset_hfcsx(cs); in hfcsx_card_msg()
1443 release_io_hfcsx(cs); in hfcsx_card_msg()
1446 inithfcsx(cs); in hfcsx_card_msg()
1452 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; in hfcsx_card_msg()
1453 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_card_msg()
1455 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in hfcsx_card_msg()
1479 struct IsdnCardState *cs = card->cs; in setup_hfcsx() local
1524 cs->hw.hfcsx.base = card->para[1] & 0xfffe; in setup_hfcsx()
1525 cs->irq = card->para[0]; in setup_hfcsx()
1526 cs->hw.hfcsx.int_s1 = 0; in setup_hfcsx()
1527 cs->dc.hfcsx.ph_state = 0; in setup_hfcsx()
1528 cs->hw.hfcsx.fifo = 255; in setup_hfcsx()
1529 if ((cs->typ == ISDN_CTYPE_HFC_SX) || in setup_hfcsx()
1530 (cs->typ == ISDN_CTYPE_HFC_SP_PCMCIA)) { in setup_hfcsx()
1531 if ((!cs->hw.hfcsx.base) || in setup_hfcsx()
1532 check_region((cs->hw.hfcsx.base), 2)) { in setup_hfcsx()
1535 cs->hw.hfcsx.base); in setup_hfcsx()
1538 request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn"); in setup_hfcsx()
1540 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF); in setup_hfcsx()
1541 byteout(cs->hw.hfcsx.base + 1, in setup_hfcsx()
1542 ((cs->hw.hfcsx.base >> 8) & 3) | 0x54); in setup_hfcsx()
1544 cs->hw.hfcsx.chip = Read_hfc(cs,HFCSX_CHIP_ID); in setup_hfcsx()
1545 switch (cs->hw.hfcsx.chip >> 4) { in setup_hfcsx()
1555 cs->hw.hfcsx.chip >> 4); in setup_hfcsx()
1556 release_region(cs->hw.hfcsx.base, 2); in setup_hfcsx()
1559 if (!ccd_sp_irqtab[cs->irq & 0xF]) { in setup_hfcsx()
1561 "HFC_SX: invalid irq %d specified\n",cs->irq & 0xF); in setup_hfcsx()
1562 release_region(cs->hw.hfcsx.base, 2); in setup_hfcsx()
1567 if (!(cs->hw.hfcsx.extra = (void *) in setup_hfcsx()
1570 release_region(cs->hw.hfcsx.base, 2); in setup_hfcsx()
1578 tmp[0], (u_int) cs->hw.hfcsx.base, in setup_hfcsx()
1579 cs->irq, HZ); in setup_hfcsx()
1580 cs->hw.hfcsx.int_m2 = 0; /* disable alle interrupts */ in setup_hfcsx()
1581 cs->hw.hfcsx.int_m1 = 0; in setup_hfcsx()
1582 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in setup_hfcsx()
1583 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in setup_hfcsx()
1587 cs->readisac = NULL; in setup_hfcsx()
1588 cs->writeisac = NULL; in setup_hfcsx()
1589 cs->readisacfifo = NULL; in setup_hfcsx()
1590 cs->writeisacfifo = NULL; in setup_hfcsx()
1591 cs->BC_Read_Reg = NULL; in setup_hfcsx()
1592 cs->BC_Write_Reg = NULL; in setup_hfcsx()
1593 cs->irq_func = &hfcsx_interrupt; in setup_hfcsx()
1595 cs->hw.hfcsx.timer.function = (void *) hfcsx_Timer; in setup_hfcsx()
1596 cs->hw.hfcsx.timer.data = (long) cs; in setup_hfcsx()
1597 cs->hw.hfcsx.b_fifo_size = 0; /* fifo size still unknown */ in setup_hfcsx()
1598 cs->hw.hfcsx.cirm = ccd_sp_irqtab[cs->irq & 0xF]; /* RAM not evaluated */ in setup_hfcsx()
1599 init_timer(&cs->hw.hfcsx.timer); in setup_hfcsx()
1601 reset_hfcsx(cs); in setup_hfcsx()
1602 cs->cardmsg = &hfcsx_card_msg; in setup_hfcsx()
1603 cs->auxcmd = &hfcsx_auxcmd; in setup_hfcsx()