Lines Matching refs:Write_hfc
64 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val) in Write_hfc() function
169 Write_hfc(cs, HFCSX_FIF_DWR, *src++); in write_fifo()
209 Write_hfc(cs, HFCSX_FIF_DWR, *src++); in write_fifo()
334 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in release_io_hfcsx()
336 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET); /* Reset On */ in release_io_hfcsx()
340 Write_hfc(cs, HFCSX_CIRM, 0); /* Reset Off */ in release_io_hfcsx()
379 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in reset_hfcsx()
383 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm ); /* Reset */ in reset_hfcsx()
387 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */ in reset_hfcsx()
398 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in reset_hfcsx()
400 Write_hfc(cs, HFCSX_CLKDEL, 0x0e); /* ST-Bit delay for TE-Mode */ in reset_hfcsx()
402 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); /* S/T Auto awake */ in reset_hfcsx()
406 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in reset_hfcsx()
410 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in reset_hfcsx()
415 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 2); /* HFC ST 2 */ in reset_hfcsx()
417 Write_hfc(cs, HFCSX_STATES, 2); /* HFC ST 2 */ in reset_hfcsx()
420 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in reset_hfcsx()
422 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in reset_hfcsx()
424 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in reset_hfcsx()
434 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in reset_hfcsx()
435 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */ in reset_hfcsx()
436 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */ in reset_hfcsx()
437 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */ in reset_hfcsx()
438 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */ in reset_hfcsx()
442 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in reset_hfcsx()
669 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0); /* HFC ST G0 */ in hfcsx_auxcmd()
672 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */ in hfcsx_auxcmd()
674 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 1); /* HFC ST G1 */ in hfcsx_auxcmd()
676 Write_hfc(cs, HFCSX_STATES, 1 | HFCSX_ACTIVATE | HFCSX_DO_ACTION); in hfcsx_auxcmd()
705 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in hfcsx_auxcmd()
706 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in hfcsx_auxcmd()
707 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in hfcsx_auxcmd()
708 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in hfcsx_auxcmd()
709 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in hfcsx_auxcmd()
710 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_auxcmd()
812 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_interrupt()
1017 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3); /* HFC ST 3 */ in HFCSX_l1hw()
1019 Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */ in HFCSX_l1hw()
1021 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
1022 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); in HFCSX_l1hw()
1026 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); in HFCSX_l1hw()
1030 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
1034 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
1039 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* tx slot */ in HFCSX_l1hw()
1040 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* rx slot */ in HFCSX_l1hw()
1044 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in HFCSX_l1hw()
1049 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* tx slot */ in HFCSX_l1hw()
1050 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* rx slot */ in HFCSX_l1hw()
1054 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in HFCSX_l1hw()
1066 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in HFCSX_l1hw()
1201 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); in mode_hfcsx()
1202 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in mode_hfcsx()
1203 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in mode_hfcsx()
1204 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in mode_hfcsx()
1205 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in mode_hfcsx()
1206 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in mode_hfcsx()
1364 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1368 Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE); in hfcsx_bh()
1370 Write_hfc(cs, HFCSX_STATES, 4); in hfcsx_bh()
1374 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1377 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_bh()
1378 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_bh()
1380 Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3); /* allow G2 -> G3 transition */ in hfcsx_bh()
1391 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1453 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_card_msg()
1455 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in hfcsx_card_msg()
1582 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in setup_hfcsx()
1583 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in setup_hfcsx()