Lines Matching refs:Write_hfc
84 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in release_io_hfcpci()
86 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */ in release_io_hfcpci()
90 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */ in release_io_hfcpci()
111 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in reset_hfcpci()
115 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */ in reset_hfcpci()
119 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */ in reset_hfcpci()
126 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in reset_hfcpci()
129 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in reset_hfcpci()
131 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_TE); /* ST-Bit delay for TE-Mode */ in reset_hfcpci()
133 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); /* S/T Auto awake */ in reset_hfcpci()
137 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in reset_hfcpci()
141 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in reset_hfcpci()
146 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 2); /* HFC ST 2 */ in reset_hfcpci()
148 Write_hfc(cs, HFCPCI_STATES, 2); /* HFC ST 2 */ in reset_hfcpci()
151 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in reset_hfcpci()
153 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in reset_hfcpci()
155 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in reset_hfcpci()
165 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in reset_hfcpci()
166 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */ in reset_hfcpci()
167 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */ in reset_hfcpci()
168 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */ in reset_hfcpci()
169 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */ in reset_hfcpci()
173 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in reset_hfcpci()
245 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_rx()
253 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_rx()
272 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_tx()
279 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_tx()
816 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_NT); /* ST-Bit delay for NT-Mode */ in hfcpci_auxcmd()
817 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 0); /* HFC ST G0 */ in hfcpci_auxcmd()
820 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); /* set NT-mode */ in hfcpci_auxcmd()
822 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 1); /* HFC ST G1 */ in hfcpci_auxcmd()
824 Write_hfc(cs, HFCPCI_STATES, 1 | HFCPCI_ACTIVATE | HFCPCI_DO_ACTION); in hfcpci_auxcmd()
854 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in hfcpci_auxcmd()
855 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in hfcpci_auxcmd()
856 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in hfcpci_auxcmd()
857 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in hfcpci_auxcmd()
858 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in hfcpci_auxcmd()
859 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_auxcmd()
860 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_auxcmd()
1018 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_interrupt()
1223 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3); /* HFC ST 3 */ in HFCPCI_l1hw()
1225 Write_hfc(cs, HFCPCI_STATES, 3); /* HFC ST 2 */ in HFCPCI_l1hw()
1227 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1228 Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION); in HFCPCI_l1hw()
1232 Write_hfc(cs, HFCPCI_STATES, HFCPCI_DO_ACTION); in HFCPCI_l1hw()
1236 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1240 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1245 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* tx slot */ in HFCPCI_l1hw()
1246 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* rx slot */ in HFCPCI_l1hw()
1250 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in HFCPCI_l1hw()
1255 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* tx slot */ in HFCPCI_l1hw()
1256 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* rx slot */ in HFCPCI_l1hw()
1260 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in HFCPCI_l1hw()
1272 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in HFCPCI_l1hw()
1421 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); in mode_hfcpci()
1422 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in mode_hfcpci()
1423 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in mode_hfcpci()
1424 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in mode_hfcpci()
1425 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in mode_hfcpci()
1426 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in mode_hfcpci()
1427 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in mode_hfcpci()
1581 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1585 Write_hfc(cs, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE); in hfcpci_bh()
1587 Write_hfc(cs, HFCPCI_STATES, 4); in hfcpci_bh()
1591 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1594 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_bh()
1595 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_bh()
1597 Write_hfc(cs, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3); /* allow G2 -> G3 transition */ in hfcpci_bh()
1608 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1670 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_card_msg()
1672 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in hfcpci_card_msg()
1764 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in setup_hfcpci()
1765 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in setup_hfcpci()