96 	return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80));  in ReadISAC()
102 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value);  in WriteISAC()
108 	readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);  in ReadISACfifo()
114 	writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);  in WriteISACfifo()
121 	return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0)));  in ReadHSCX()
127 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value);  in WriteHSCX()
135 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK,  in set_ipac_active()
144 	cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0))
146 	cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0), data)
148 	cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
150 	cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
164 	ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);  in bkm_interrupt_ipac()
171 		val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40);  in bkm_interrupt_ipac()
183 		val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80);  in bkm_interrupt_ipac()
192 	ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);  in bkm_interrupt_ipac()
201 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);  in bkm_interrupt_ipac()
202 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);  in bkm_interrupt_ipac()
438 	cs->hw.ax.data_adr = cs->hw.ax.base + 4;  in setup_sct_quadro()
445 	       cs->hw.ax.data_adr,  in setup_sct_quadro()
464 		readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));  in setup_sct_quadro()