Lines Matching refs:FPGA_PORT
15 #define FPGA_PORT 0x6E macro
82 UxCardPortIoOutW(NULL, (byte *) addr, FPGA_PORT, baseval &~Mask_PROGRAM); // PROGRAM low pulse in FPGA_Download()
83 UxCardPortIoOutW(NULL, (byte *) addr, FPGA_PORT, baseval); // release in FPGA_Download()
87 if (UxCardPortIoInW(NULL, (byte *) addr, FPGA_PORT) &Mask_DONE) in FPGA_Download()
114 UxCardPortIoOutW(NULL, (byte *) addr, FPGA_PORT, baseval); in FPGA_Download()
115 UxCardPortIoOutW(NULL, (byte *) addr, FPGA_PORT, baseval | Mask_CCLK); // set CCLK hi in FPGA_Download()
116 UxCardPortIoOutW(NULL, (byte *) addr, FPGA_PORT, baseval); // set CCLK lo in FPGA_Download()
123 UxCardPortIoOutW(NULL, (byte *) addr, FPGA_PORT, baseval | Mask_CCLK); // set CCLK hi in FPGA_Download()
124 UxCardPortIoOutW(NULL, (byte *) addr, FPGA_PORT, baseval); // set CCLK lo in FPGA_Download()
129 if (UxCardPortIoInW(NULL, (byte *) addr, FPGA_PORT) &Mask_DONE) in FPGA_Download()
135 … DPRINTF(("divas: FPGA download failed - 0x%x", UxCardPortIoInW(NULL, (byte *) addr, FPGA_PORT))); in FPGA_Download()