245 		SCCwrite(INT_AND_DMA_REG, 0);  in mvme147_scc_init()
247 		SCCwrite(INT_VECTOR_REG, MVME147_IRQ_SCC_BASE);  in mvme147_scc_init()
249 		SCCwrite(MASTER_INT_CTRL, MIC_VEC_INCL_STAT);  in mvme147_scc_init()
272 		SCCwrite(INT_AND_DMA_REG, 0);  in mvme147_scc_init()
315 		SCCwrite(INT_AND_DMA_REG, 0);  in mvme162_scc_init()
317 		SCCwrite(INT_VECTOR_REG, MVME162_IRQ_SCC_BASE);  in mvme162_scc_init()
319 		SCCwrite(MASTER_INT_CTRL, MIC_VEC_INCL_STAT);  in mvme162_scc_init()
343 		SCCwrite(INT_AND_DMA_REG, 0);  in mvme162_scc_init()
383 		SCCwrite(INT_AND_DMA_REG, 0);  in bvme6000_scc_init()
385 		SCCwrite(INT_VECTOR_REG, BVME_IRQ_SCC_BASE);  in bvme6000_scc_init()
387 		SCCwrite(MASTER_INT_CTRL, MIC_VEC_INCL_STAT);  in bvme6000_scc_init()
411 		SCCwrite(INT_AND_DMA_REG, 0);  in bvme6000_scc_init()
499 		SCCwrite(COMMAND_REG, CR_ERROR_RESET);  in scc_spcond_int()
528 		  SCCwrite(COMMAND_REG, CR_ERROR_RESET);  in scc_spcond_int()
546 		SCCwrite(COMMAND_REG, CR_TX_PENDING_RESET);  in scc_tx_int()
552 			SCCwrite(TX_DATA_REG, port->x_char);  in scc_tx_int()
559 			SCCwrite(TX_DATA_REG, port->gs.xmit_buf[port->gs.xmit_tail++]);  in scc_tx_int()
569 		SCCwrite(COMMAND_REG, CR_TX_PENDING_RESET);   /* disable tx_int on next tx underrun? */  in scc_tx_int()
609 	SCCwrite(COMMAND_REG, CR_EXTSTAT_RESET);  in scc_stat_int()
768 	SCCwrite(TIMER_LOW_REG, brgval & 0xff);  in scc_set_real_termios()
769 	SCCwrite(TIMER_HIGH_REG, (brgval >> 8) & 0xff);  in scc_set_real_termios()
828 	SCCwrite(TX_CTRL_REG, t);  in scc_setsignals()
919 				SCCwrite(mvme_init_tab[i].reg, mvme_init_tab[i].val);  in scc_open()
925 				SCCwrite(bvme_init_tab[i].reg, bvme_init_tab[i].val);  in scc_open()