410 #define TXDMA 	0x20  macro
2198 	write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */  in isr_txeom()
2199 	write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */  in isr_txeom()
2200 	write_reg(info, TXDMA + DCMD, SWABORT);	/* reset/init DMA channel */  in isr_txeom()
2350 	write_reg(info, TXDMA + DIR, 0x00);	/* disable Tx DMA IRQs */  in isr_txdmaok()
2351 	write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */  in isr_txdmaok()
2352 	write_reg(info, TXDMA + DCMD, SWABORT);	/* reset/init DMA channel */  in isr_txdmaok()
2369 	unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;  in isr_txdmaerror()
2372 	write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));  in isr_txdmaerror()
2966 		write_reg(info, TXDMA + DSR, 0);		/* disable DMA channel */  in tx_abort()
2967 		write_reg(info, TXDMA + DCMD, SWABORT);	/* reset/init DMA channel */  in tx_abort()
4250 			write_reg(info, TXDMA + DSR, 0); 		/* disable DMA channel */  in tx_start()
4251 			write_reg(info, TXDMA + DCMD, SWABORT);	/* reset/init DMA channel */  in tx_start()
4254 			write_reg16(info, TXDMA + CDA,  in tx_start()
4258 			write_reg16(info, TXDMA + EDA,  in tx_start()
4267 			write_reg(info, TXDMA + DIR, 0x40);		/* enable Tx DMA interrupts (EOM) */  in tx_start()
4268 			write_reg(info, TXDMA + DSR, 0xf2);		/* clear Tx DMA IRQs, enable Tx DMA */  in tx_start()
4294 	write_reg(info, TXDMA + DSR, 0);		/* disable DMA channel */  in tx_stop()
4295 	write_reg(info, TXDMA + DCMD, SWABORT);	/* reset/init DMA channel */  in tx_stop()
4550 	write_reg(info, TXDMA + DIR, 0);  in hdlc_mode()
4692 	write_reg(info, TXDMA + DMR, 0x14);  in hdlc_mode()
4700 	write_reg(info, TXDMA + CPB,  in hdlc_mode()