1678 	unsigned char RegValue;  in set_break()  local
1690 	RegValue = read_reg(info, CTL);  in set_break()
1692 		RegValue |= BIT3;  in set_break()
1694 		RegValue &= ~BIT3;  in set_break()
1695 	write_reg(info, CTL, RegValue);  in set_break()
4401   	unsigned char RegValue;  in async_mode()  local
4416 	RegValue = 0x00;  in async_mode()
4418 		RegValue |= BIT1;  in async_mode()
4419 	write_reg(info, MD0, RegValue);  in async_mode()
4430 	RegValue = 0x40;  in async_mode()
4432 	case 7: RegValue |= BIT4 + BIT2; break;  in async_mode()
4433 	case 6: RegValue |= BIT5 + BIT3; break;  in async_mode()
4434 	case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;  in async_mode()
4437 		RegValue |= BIT1;  in async_mode()
4439 			RegValue |= BIT0;  in async_mode()
4441 	write_reg(info, MD1, RegValue);  in async_mode()
4450 	RegValue = 0x00;  in async_mode()
4451 	write_reg(info, MD2, RegValue);  in async_mode()
4459 	RegValue=BIT6;  in async_mode()
4460 	write_reg(info, RXS, RegValue);  in async_mode()
4468 	RegValue=BIT6;  in async_mode()
4469 	write_reg(info, TXS, RegValue);  in async_mode()
4513 	RegValue = 0x10;  in async_mode()
4515 		RegValue |= 0x01;  in async_mode()
4516 	write_reg(info, CTL, RegValue);  in async_mode()
4540 	unsigned char RegValue;  in hdlc_mode()  local
4564 	RegValue = 0x81;  in hdlc_mode()
4566 		RegValue |= BIT4;  in hdlc_mode()
4568 		RegValue |= BIT4;  in hdlc_mode()
4570 		RegValue |= BIT2 + BIT1;  in hdlc_mode()
4571 	write_reg(info, MD0, RegValue);  in hdlc_mode()
4582 	RegValue = 0x00;  in hdlc_mode()
4583 	write_reg(info, MD1, RegValue);  in hdlc_mode()
4595 	RegValue = 0x00;  in hdlc_mode()
4597 	case HDLC_ENCODING_NRZI:	  RegValue |= BIT5; break;  in hdlc_mode()
4598 	case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */  in hdlc_mode()
4599 	case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */  in hdlc_mode()
4600 	case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; 	/* aka Manchester */  in hdlc_mode()
4609 		RegValue |= BIT3;  in hdlc_mode()
4614 		RegValue |= BIT4;  in hdlc_mode()
4616 	write_reg(info, MD2, RegValue);  in hdlc_mode()
4625 	RegValue=0;  in hdlc_mode()
4627 		RegValue |= BIT6;  in hdlc_mode()
4629 		RegValue |= BIT6 + BIT5;  in hdlc_mode()
4630 	write_reg(info, RXS, RegValue);  in hdlc_mode()
4638 	RegValue=0;  in hdlc_mode()
4640 		RegValue |= BIT6;  in hdlc_mode()
4642 		RegValue |= BIT6 + BIT5;  in hdlc_mode()
4643 	write_reg(info, TXS, RegValue);  in hdlc_mode()
4721 	RegValue = 0x10;  in hdlc_mode()
4723 		RegValue |= 0x01;  in hdlc_mode()
4724 	write_reg(info, CTL, RegValue);  in hdlc_mode()
4742 	unsigned char RegValue = 0xff;  in tx_set_idle()  local
4746 	case HDLC_TXIDLE_FLAGS:			RegValue = 0x7e; break;  in tx_set_idle()
4747 	case HDLC_TXIDLE_ALT_ZEROS_ONES:	RegValue = 0xaa; break;  in tx_set_idle()
4748 	case HDLC_TXIDLE_ZEROS:			RegValue = 0x00; break;  in tx_set_idle()
4749 	case HDLC_TXIDLE_ONES:			RegValue = 0xff; break;  in tx_set_idle()
4750 	case HDLC_TXIDLE_ALT_MARK_SPACE:	RegValue = 0xaa; break;  in tx_set_idle()
4751 	case HDLC_TXIDLE_SPACE:			RegValue = 0x00; break;  in tx_set_idle()
4752 	case HDLC_TXIDLE_MARK:			RegValue = 0xff; break;  in tx_set_idle()
4755 	write_reg(info, IDL, RegValue);  in tx_set_idle()
4791 	unsigned char RegValue;  in set_signals()  local
4794 	RegValue = read_reg(info, CTL);  in set_signals()
4796 		RegValue &= ~BIT0;  in set_signals()
4798 		RegValue |= BIT0;  in set_signals()
4799 	write_reg(info, CTL, RegValue);  in set_signals()