Lines Matching refs:BYTE
49 BYTE cc_init_status; /* 0x00 Initialisation status */
50 BYTE cc_mem_size; /* 0x01 Size of memory on card */
53 BYTE cc_isr_count; /* 0x06 Count when ISR is run */
54 BYTE cc_main_count; /* 0x07 Count when main loop is run */
57 BYTE cc_int_set_count; /* 0x0C Count when host interrupt is set */
58 BYTE cc_rfu[0x80 - 0x0D]; /* 0x0D Pad structure to 128 bytes (0x80) */
63 #define ADAPTERS_FOUND (BYTE)0x01
64 #define NO_ADAPTERS_FOUND (BYTE)0xFF
67 #define SX_MEMORY_SIZE (BYTE)0x40
84 BYTE mc_type; /* 0x02 Type of TA in terms of number of channels */
85 BYTE mc_mod_no; /* 0x03 Module number on SI bus cable (0 closest to card) */
86 BYTE mc_dtr; /* 0x04 Private DTR copy (TA only) */
87 BYTE mc_rfu1; /* 0x05 Reserved */
89 BYTE mc_chip; /* 0x08 Chip type / number of ports */
90 BYTE mc_current_uart; /* 0x09 Current uart selected for this module */
97 BYTE mc_opens1; /* 0x1C Number of open ports on first four ports on MTA/SXDC */
98 BYTE mc_opens2; /* 0x1D Number of open ports on second four ports on MTA/SXDC */
99 BYTE mc_mods; /* 0x1E Types of connector module attached to MTA/SXDC */
100 BYTE mc_rev1; /* 0x1F Revision of first CD1400 on MTA/SXDC */
101 BYTE mc_rev2; /* 0x20 Revision of second CD1400 on MTA/SXDC */
102 BYTE mc_mtaasic_rev; /* 0x21 Revision of MTA ASIC 1..4 -> A, B, C, D */
103 BYTE mc_rfu3[0x100 - 0x22]; /* 0x22 Pad structure to 256 bytes (0x100) */
108 #define FOUR_PORTS (BYTE)4
109 #define EIGHT_PORTS (BYTE)8
113 #define TA (BYTE)0
116 #define TA4_ASIC (BYTE)0x0A
117 #define TA8_ASIC (BYTE)0x0B
118 #define MTA_CD1400 (BYTE)0x28
119 #define SXDC (BYTE)0x48
157 BYTE type; /* 0x06 Chip type / number of ports (copy of mc_chip) */
158 BYTE chan_number; /* 0x07 Channel number on the TA/MTA/SXDC */
160 BYTE hi_rxipos; /* 0x0A Receive buffer input index */
161 BYTE hi_rxopos; /* 0x0B Receive buffer output index */
162 BYTE hi_txopos; /* 0x0C Transmit buffer output index */
163 BYTE hi_txipos; /* 0x0D Transmit buffer input index */
164 BYTE hi_hstat; /* 0x0E Command register */
165 BYTE dtr_bit; /* 0x0F INTERNAL DTR control byte (TA only) */
166 BYTE txon; /* 0x10 INTERNAL copy of hi_txon */
167 BYTE txoff; /* 0x11 INTERNAL copy of hi_txoff */
168 BYTE rxon; /* 0x12 INTERNAL copy of hi_rxon */
169 BYTE rxoff; /* 0x13 INTERNAL copy of hi_rxoff */
170 BYTE hi_mr1; /* 0x14 Mode Register 1 (databits,parity,RTS rx flow)*/
171 BYTE hi_mr2; /* 0x15 Mode Register 2 (stopbits,local,CTS tx flow)*/
172 BYTE hi_csr; /* 0x16 Clock Select Register (baud rate) */
173 BYTE hi_op; /* 0x17 Modem Output Signal */
174 BYTE hi_ip; /* 0x18 Modem Input Signal */
175 BYTE hi_state; /* 0x19 Channel status */
176 BYTE hi_prtcl; /* 0x1A Channel protocol (flow control) */
177 BYTE hi_txon; /* 0x1B Transmit XON character */
178 BYTE hi_txoff; /* 0x1C Transmit XOFF character */
179 BYTE hi_rxon; /* 0x1D Receive XON character */
180 BYTE hi_rxoff; /* 0x1E Receive XOFF character */
181 BYTE close_prev; /* 0x1F INTERNAL channel previously closed flag */
182 BYTE hi_break; /* 0x20 Break and error control */
183 BYTE break_state; /* 0x21 INTERNAL copy of hi_break */
184 BYTE hi_mask; /* 0x22 Mask for received data */
185 BYTE mask; /* 0x23 INTERNAL copy of hi_mask */
186 BYTE mod_type; /* 0x24 MTA/SXDC hardware module type */
187 BYTE ccr_state; /* 0x25 INTERNAL MTA/SXDC state of CCR register */
188 BYTE ip_mask; /* 0x26 Input handshake mask */
189 BYTE hi_parallel; /* 0x27 Parallel port flag */
190 BYTE par_error; /* 0x28 Error code for parallel loopback test */
191 BYTE any_sent; /* 0x29 INTERNAL data sent flag */
192 BYTE asic_txfifo_size; /* 0x2A INTERNAL SXDC transmit FIFO size */
193 BYTE rfu1[2]; /* 0x2B Reserved */
194 BYTE csr; /* 0x2D INTERNAL copy of hi_csr */
200 BYTE prtcl; /* 0x30 INTERNAL copy of hi_prtcl */
201 BYTE mr1; /* 0x31 INTERNAL copy of hi_mr1 */
202 BYTE mr2; /* 0x32 INTERNAL copy of hi_mr2 */
203 BYTE hi_txbaud; /* 0x33 Extended transmit baud rate (SXDC only if((hi_csr&0x0F)==0x0F) */
204 BYTE hi_rxbaud; /* 0x34 Extended receive baud rate (SXDC only if((hi_csr&0xF0)==0xF0) */
205 BYTE txbreak_state; /* 0x35 INTERNAL MTA/SXDC transmit break state */
206 BYTE txbaud; /* 0x36 INTERNAL copy of hi_txbaud */
207 BYTE rxbaud; /* 0x37 INTERNAL copy of hi_rxbaud */
212 BYTE rfu2[TX_BUFF_OFFSET - 0x40]; /* 0x40 Reserved until hi_txbuf */
213 BYTE hi_txbuf[BUFFER_SIZE]; /* 0x060 Transmit buffer */
214 BYTE hi_rxbuf[BUFFER_SIZE]; /* 0x160 Receive buffer */
215 BYTE rfu3[0x300 - 0x260]; /* 0x260 Reserved until 768 bytes (0x300) */