Lines Matching refs:base_addr
304 write_cy_cmd(volatile u_char *base_addr, u_char cmd) in write_cy_cmd() argument
312 if (base_addr[CyCCR] == 0){ in write_cy_cmd()
325 base_addr[CyCCR] = cmd; in write_cy_cmd()
338 volatile unsigned char *base_addr = (unsigned char *)BASE_ADDR; in cy_stop() local
352 base_addr[CyCAR] = (u_char)(channel); /* index channel */ in cy_stop()
353 base_addr[CyIER] &= ~(CyTxMpty|CyTxRdy); in cy_stop()
363 volatile unsigned char *base_addr = (unsigned char *)BASE_ADDR; in cy_start() local
377 base_addr[CyCAR] = (u_char)(channel); in cy_start()
378 base_addr[CyIER] |= CyTxMpty; in cy_start()
409 volatile unsigned char *base_addr = (unsigned char *)BASE_ADDR; in cd2401_rxerr_interrupt() local
415 channel = (u_short ) (base_addr[CyLICR] >> 2); in cd2401_rxerr_interrupt()
419 if ((err = base_addr[CyRISR]) & CyTIMEOUT) { in cd2401_rxerr_interrupt()
421 base_addr[CyREOIR] = CyNOTRANS; in cd2401_rxerr_interrupt()
428 if ((rfoc = base_addr[CyRFOC]) != 0) in cd2401_rxerr_interrupt()
429 data = base_addr[CyRDR]; in cd2401_rxerr_interrupt()
435 base_addr[CyREOIR] = rfoc ? 0 : CyNOTRANS; in cd2401_rxerr_interrupt()
441 base_addr[CyREOIR] = rfoc ? 0 : CyNOTRANS; in cd2401_rxerr_interrupt()
491 base_addr[CyREOIR] = rfoc ? 0 : CyNOTRANS; in cd2401_rxerr_interrupt()
498 volatile unsigned char *base_addr = (unsigned char *)BASE_ADDR; in cd2401_modem_interrupt() local
505 channel = (u_short ) (base_addr[CyLICR] >> 2); in cd2401_modem_interrupt()
509 mdm_change = base_addr[CyMISR]; in cd2401_modem_interrupt()
510 mdm_status = base_addr[CyMSVR1]; in cd2401_modem_interrupt()
532 base_addr[CyIER] |= CyTxMpty; in cd2401_modem_interrupt()
539 base_addr[CyIER] &= ~(CyTxMpty|CyTxRdy); in cd2401_modem_interrupt()
546 base_addr[CyMEOIR] = 0; in cd2401_modem_interrupt()
553 volatile unsigned char *base_addr = (unsigned char *)BASE_ADDR; in cd2401_tx_interrupt() local
559 channel = (u_short ) (base_addr[CyLICR] >> 2); in cd2401_tx_interrupt()
571 base_addr[CyIER] &= ~(CyTxMpty|CyTxRdy); in cd2401_tx_interrupt()
572 base_addr[CyTEOIR] = CyNOTRANS; in cd2401_tx_interrupt()
577 base_addr[CyIER] &= ~(CyTxMpty|CyTxRdy); in cd2401_tx_interrupt()
581 base_addr[CyTEOIR] = CyNOTRANS; in cd2401_tx_interrupt()
586 saved_cnt = char_count = base_addr[CyTFTC]; in cd2401_tx_interrupt()
590 base_addr[CyTDR] = outch; in cd2401_tx_interrupt()
605 base_addr[CyTDR] = 0; /* start break */ in cd2401_tx_interrupt()
606 base_addr[CyTDR] = 0x81; in cd2401_tx_interrupt()
607 base_addr[CyTDR] = 0; /* delay a bit */ in cd2401_tx_interrupt()
608 base_addr[CyTDR] = 0x82; in cd2401_tx_interrupt()
609 base_addr[CyTDR] = info->x_break*200/HZ; in cd2401_tx_interrupt()
610 base_addr[CyTDR] = 0; /* terminate break */ in cd2401_tx_interrupt()
611 base_addr[CyTDR] = 0x83; in cd2401_tx_interrupt()
618 base_addr[CyIER] &= ~(CyTxMpty|CyTxRdy); in cd2401_tx_interrupt()
622 base_addr[CyIER] &= ~(CyTxMpty|CyTxRdy); in cd2401_tx_interrupt()
626 base_addr[CyIER] &= ~(CyTxMpty|CyTxRdy); in cd2401_tx_interrupt()
645 base_addr[CyTDR] = outch; in cd2401_tx_interrupt()
652 base_addr[CyTDR] = outch; in cd2401_tx_interrupt()
653 base_addr[CyTDR] = 0; in cd2401_tx_interrupt()
665 base_addr[CyTEOIR] = (char_count != saved_cnt) ? 0 : CyNOTRANS; in cd2401_tx_interrupt()
673 volatile unsigned char *base_addr = (unsigned char *)BASE_ADDR; in cd2401_rx_interrupt() local
680 channel = (u_short ) (base_addr[CyLICR] >> 2); in cd2401_rx_interrupt()
683 save_cnt = char_count = base_addr[CyRFOC]; in cd2401_rx_interrupt()
688 data = base_addr[CyRDR]; in cd2401_rx_interrupt()
697 data = base_addr[CyRDR]; in cd2401_rx_interrupt()
711 data = base_addr[CyRDR]; in cd2401_rx_interrupt()
725 base_addr[CyREOIR] = save_cnt ? 0 : CyNOTRANS; in cd2401_rx_interrupt()
788 volatile unsigned char *base_addr = (unsigned char *)BASE_ADDR; in startup() local
817 base_addr[CyCAR] = (u_char)channel; in startup()
818 write_cy_cmd(base_addr,CyENB_RCVR|CyENB_XMTR); in startup()
820 base_addr[CyCAR] = (u_char)channel; /* !!! Is this needed? */ in startup()
821 base_addr[CyMSVR1] = CyRTS; in startup()
823 base_addr[CyMSVR2] = CyDTR; in startup()
827 printk(" status: 0x%x, 0x%x\n", base_addr[CyMSVR1], base_addr[CyMSVR2]); in startup()
830 base_addr[CyIER] |= CyRxData; in startup()
850 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in start_xmit() local
855 base_addr[CyCAR] = channel; in start_xmit()
856 base_addr[CyIER] |= CyTxMpty; in start_xmit()
868 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in shutdown() local
894 base_addr[CyCAR] = (u_char)channel; in shutdown()
896 base_addr[CyMSVR1] = 0; in shutdown()
898 base_addr[CyMSVR2] = 0; in shutdown()
901 printk(" status: 0x%x, 0x%x\n", base_addr[CyMSVR1], base_addr[CyMSVR2]); in shutdown()
904 write_cy_cmd(base_addr,CyDIS_RCVR); in shutdown()
927 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in config_setup() local
1005 base_addr[CyCAR] = (u_char)channel; in config_setup()
1007 if (base_addr[CyIER] & CyMdmCh) in config_setup()
1008 base_addr[CyIER] &= ~CyMdmCh; /* without modem intr */ in config_setup()
1010 if (base_addr[CyCOR4] & (CyDSR|CyCTS|CyDCD)) in config_setup()
1011 base_addr[CyCOR4] &= ~(CyDSR|CyCTS|CyDCD); in config_setup()
1013 if (base_addr[CyCOR5] & (CyDSR|CyCTS|CyDCD)) in config_setup()
1014 base_addr[CyCOR5] &= ~(CyDSR|CyCTS|CyDCD); in config_setup()
1016 if ((base_addr[CyIER] & CyMdmCh) != CyMdmCh) in config_setup()
1017 base_addr[CyIER] |= CyMdmCh; /* with modem intr */ in config_setup()
1019 if ((base_addr[CyCOR4] & (CyDSR|CyCTS|CyDCD)) != (CyDSR|CyCTS|CyDCD)) in config_setup()
1020 base_addr[CyCOR4] |= CyDSR|CyCTS|CyDCD; in config_setup()
1022 if ((base_addr[CyCOR5] & (CyDSR|CyCTS|CyDCD)) != (CyDSR|CyCTS|CyDCD)) in config_setup()
1023 base_addr[CyCOR5] |= CyDSR|CyCTS|CyDCD; in config_setup()
1080 base_addr[CyCAR] = (u_char)channel; in config_setup()
1083 if (base_addr[CyLICR] != channel << 2) in config_setup()
1084 base_addr[CyLICR] = channel << 2; in config_setup()
1085 if (base_addr[CyLIVR] != 0x5c) in config_setup()
1086 base_addr[CyLIVR] = 0x5c; in config_setup()
1090 if (base_addr[CyCOR1] != info->cor1) in config_setup()
1092 if (base_addr[CyTCOR] != info->tco) in config_setup()
1093 base_addr[CyTCOR] = info->tco; in config_setup()
1094 if (base_addr[CyTBPR] != info->tbpr) in config_setup()
1095 base_addr[CyTBPR] = info->tbpr; in config_setup()
1096 if (base_addr[CyRCOR] != info->rco) in config_setup()
1097 base_addr[CyRCOR] = info->rco; in config_setup()
1098 if (base_addr[CyRBPR] != info->rbpr) in config_setup()
1099 base_addr[CyRBPR] = info->rbpr; in config_setup()
1103 if (base_addr[CySCHR1] != START_CHAR(info->tty)) in config_setup()
1104 base_addr[CySCHR1] = START_CHAR(info->tty); in config_setup()
1105 if (base_addr[CySCHR2] != STOP_CHAR(info->tty)) in config_setup()
1106 base_addr[CySCHR2] = STOP_CHAR(info->tty); in config_setup()
1107 if (base_addr[CySCRL] != START_CHAR(info->tty)) in config_setup()
1108 base_addr[CySCRL] = START_CHAR(info->tty); in config_setup()
1109 if (base_addr[CySCRH] != START_CHAR(info->tty)) in config_setup()
1110 base_addr[CySCRH] = START_CHAR(info->tty); in config_setup()
1111 if (base_addr[CyCOR1] != info->cor1) in config_setup()
1112 base_addr[CyCOR1] = info->cor1; in config_setup()
1113 if (base_addr[CyCOR2] != info->cor2) in config_setup()
1114 base_addr[CyCOR2] = info->cor2; in config_setup()
1115 if (base_addr[CyCOR3] != info->cor3) in config_setup()
1116 base_addr[CyCOR3] = info->cor3; in config_setup()
1117 if (base_addr[CyCOR4] != info->cor4) in config_setup()
1118 base_addr[CyCOR4] = info->cor4; in config_setup()
1119 if (base_addr[CyCOR5] != info->cor5) in config_setup()
1120 base_addr[CyCOR5] = info->cor5; in config_setup()
1121 if (base_addr[CyCOR6] != info->cor6) in config_setup()
1122 base_addr[CyCOR6] = info->cor6; in config_setup()
1123 if (base_addr[CyCOR7] != info->cor7) in config_setup()
1124 base_addr[CyCOR7] = info->cor7; in config_setup()
1127 write_cy_cmd(base_addr,CyINIT_CHAN); in config_setup()
1129 base_addr[CyCAR] = (u_char)channel; /* !!! Is this needed? */ in config_setup()
1133 if (base_addr[CyRTPRL] != ti) in config_setup()
1134 base_addr[CyRTPRL] = ti; in config_setup()
1135 if (base_addr[CyRTPRH] != 0) in config_setup()
1136 base_addr[CyRTPRH] = 0; in config_setup()
1140 if ((base_addr[CyMSVR2] & CyDTR) == CyDTR) in config_setup()
1141 base_addr[CyMSVR2] = 0; in config_setup()
1144 printk(" status: 0x%x, 0x%x\n", base_addr[CyMSVR1], base_addr[CyMSVR2]); in config_setup()
1147 if ((base_addr[CyMSVR2] & CyDTR) != CyDTR) in config_setup()
1148 base_addr[CyMSVR2] = CyDTR; in config_setup()
1151 printk(" status: 0x%x, 0x%x\n", base_addr[CyMSVR1], base_addr[CyMSVR2]); in config_setup()
1198 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in cy_flush_chars() local
1215 base_addr[CyCAR] = channel; in cy_flush_chars()
1216 base_addr[CyIER] |= CyTxMpty; in cy_flush_chars()
1369 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in cy_throttle() local
1392 base_addr[CyCAR] = (u_char)channel; in cy_throttle()
1393 base_addr[CyMSVR1] = 0; in cy_throttle()
1405 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in cy_unthrottle() local
1428 base_addr[CyCAR] = (u_char)channel; in cy_unthrottle()
1429 base_addr[CyMSVR1] = CyRTS; in cy_unthrottle()
1505 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in get_modem_info() local
1513 base_addr[CyCAR] = (u_char)channel; in get_modem_info()
1514 status = base_addr[CyMSVR1] | base_addr[CyMSVR2]; in get_modem_info()
1530 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in set_modem_info() local
1542 base_addr[CyCAR] = (u_char)channel; in set_modem_info()
1543 base_addr[CyMSVR1] = CyRTS; in set_modem_info()
1548 base_addr[CyCAR] = (u_char)channel; in set_modem_info()
1550 base_addr[CyMSVR2] = CyDTR; in set_modem_info()
1553 printk(" status: 0x%x, 0x%x\n", base_addr[CyMSVR1], base_addr[CyMSVR2]); in set_modem_info()
1561 base_addr[CyCAR] = (u_char)channel; in set_modem_info()
1562 base_addr[CyMSVR1] = 0; in set_modem_info()
1567 base_addr[CyCAR] = (u_char)channel; in set_modem_info()
1569 base_addr[CyMSVR2] = 0; in set_modem_info()
1572 printk(" status: 0x%x, 0x%x\n", base_addr[CyMSVR1], base_addr[CyMSVR2]); in set_modem_info()
1580 base_addr[CyCAR] = (u_char)channel; in set_modem_info()
1581 base_addr[CyMSVR1] = CyRTS; in set_modem_info()
1585 base_addr[CyCAR] = (u_char)channel; in set_modem_info()
1586 base_addr[CyMSVR1] = 0; in set_modem_info()
1591 base_addr[CyCAR] = (u_char)channel; in set_modem_info()
1593 base_addr[CyMSVR2] = CyDTR; in set_modem_info()
1596 printk(" status: 0x%x, 0x%x\n", base_addr[CyMSVR1], base_addr[CyMSVR2]); in set_modem_info()
1601 base_addr[CyCAR] = (u_char)channel; in set_modem_info()
1603 base_addr[CyMSVR2] = 0; in set_modem_info()
1606 printk(" status: 0x%x, 0x%x\n", base_addr[CyMSVR1], base_addr[CyMSVR2]); in set_modem_info()
1644 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in set_threshold() local
1654 base_addr[CyCOR4] = info->cor4; in set_threshold()
1661 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in get_threshold() local
1667 tmp = base_addr[CyCOR4] & CyREC_FIFO; in get_threshold()
1692 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in set_timeout() local
1701 base_addr[CyRTPRL] = value & 0xff; in set_timeout()
1702 base_addr[CyRTPRH] = (value >> 8) & 0xff; in set_timeout()
1709 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in get_timeout() local
1715 tmp = base_addr[CyRTPRL]; in get_timeout()
1978 volatile u_char *base_addr = (u_char *)BASE_ADDR; in block_til_ready() local
2051 base_addr[CyCAR] = (u_char)channel; in block_til_ready()
2052 base_addr[CyMSVR1] = CyRTS; in block_til_ready()
2054 base_addr[CyMSVR2] = CyDTR; in block_til_ready()
2057 printk(" status: 0x%x, 0x%x\n", base_addr[CyMSVR1], base_addr[CyMSVR2]); in block_til_ready()
2072 base_addr[CyCAR] = (u_char)channel; in block_til_ready()
2077 || (base_addr[CyMSVR1] & CyDCD))) { in block_til_ready()
2221 volatile unsigned char* base_addr = (u_char *)BASE_ADDR; in mvme167_serial_console_setup() local
2234 base_addr[CyCAR] = 0; in mvme167_serial_console_setup()
2236 rcor = base_addr[CyRCOR] << 5; in mvme167_serial_console_setup()
2237 rbpr = base_addr[CyRBPR]; in mvme167_serial_console_setup()
2251 if(base_addr[CyCCR] != 0x00){ in mvme167_serial_console_setup()
2257 base_addr[CyCCR] = CyCHIP_RESET; /* Reset the chip */ in mvme167_serial_console_setup()
2260 if(base_addr[CyGFRCR] == 0x00){ in mvme167_serial_console_setup()
2271 base_addr[CyTPR] = 10; in mvme167_serial_console_setup()
2273 base_addr[CyPILR1] = 0x01; /* Interrupt level for modem change */ in mvme167_serial_console_setup()
2274 base_addr[CyPILR2] = 0x02; /* Interrupt level for tx ints */ in mvme167_serial_console_setup()
2275 base_addr[CyPILR3] = 0x03; /* Interrupt level for rx ints */ in mvme167_serial_console_setup()
2284 base_addr[CyCAR] = (u_char)ch; in mvme167_serial_console_setup()
2285 base_addr[CyIER] = 0; in mvme167_serial_console_setup()
2286 base_addr[CyCMR] = CyASYNC; in mvme167_serial_console_setup()
2287 base_addr[CyLICR] = (u_char)ch << 2; in mvme167_serial_console_setup()
2288 base_addr[CyLIVR] = 0x5c; in mvme167_serial_console_setup()
2289 base_addr[CyTCOR] = baud_co[spd]; in mvme167_serial_console_setup()
2290 base_addr[CyTBPR] = baud_bpr[spd]; in mvme167_serial_console_setup()
2291 base_addr[CyRCOR] = baud_co[spd] >> 5; in mvme167_serial_console_setup()
2292 base_addr[CyRBPR] = baud_bpr[spd]; in mvme167_serial_console_setup()
2293 base_addr[CySCHR1] = 'Q' & 0x1f; in mvme167_serial_console_setup()
2294 base_addr[CySCHR2] = 'X' & 0x1f; in mvme167_serial_console_setup()
2295 base_addr[CySCRL] = 0; in mvme167_serial_console_setup()
2296 base_addr[CySCRH] = 0; in mvme167_serial_console_setup()
2297 base_addr[CyCOR1] = Cy_8_BITS | CyPARITY_NONE; in mvme167_serial_console_setup()
2298 base_addr[CyCOR2] = 0; in mvme167_serial_console_setup()
2299 base_addr[CyCOR3] = Cy_1_STOP; in mvme167_serial_console_setup()
2300 base_addr[CyCOR4] = baud_cor4[spd]; in mvme167_serial_console_setup()
2301 base_addr[CyCOR5] = 0; in mvme167_serial_console_setup()
2302 base_addr[CyCOR6] = 0; in mvme167_serial_console_setup()
2303 base_addr[CyCOR7] = 0; in mvme167_serial_console_setup()
2304 base_addr[CyRTPRL] = 2; in mvme167_serial_console_setup()
2305 base_addr[CyRTPRH] = 0; in mvme167_serial_console_setup()
2306 base_addr[CyMSVR1] = 0; in mvme167_serial_console_setup()
2307 base_addr[CyMSVR2] = 0; in mvme167_serial_console_setup()
2308 write_cy_cmd(base_addr,CyINIT_CHAN|CyDIS_RCVR|CyDIS_XMTR); in mvme167_serial_console_setup()
2315 base_addr[CyMSVR1] = CyRTS; in mvme167_serial_console_setup()
2316 base_addr[CyMSVR2] = CyDTR; in mvme167_serial_console_setup()
2317 base_addr[CyIER] = CyRxData; in mvme167_serial_console_setup()
2318 write_cy_cmd(base_addr,CyENB_RCVR|CyENB_XMTR); in mvme167_serial_console_setup()
2324 printk("CD2401 initialised, chip is rev 0x%02x\n", base_addr[CyGFRCR]); in mvme167_serial_console_setup()
2567 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in show_status() local
2599 printk(" CyGFRCR %x\n", base_addr[CyGFRCR]); in show_status()
2600 printk(" CyCAR %x\n", base_addr[CyCAR]); in show_status()
2601 printk(" CyRISR %x\n", base_addr[CyRISR]); in show_status()
2602 printk(" CyTISR %x\n", base_addr[CyTISR]); in show_status()
2603 printk(" CyMISR %x\n", base_addr[CyMISR]); in show_status()
2604 printk(" CyRIR %x\n", base_addr[CyRIR]); in show_status()
2605 printk(" CyTIR %x\n", base_addr[CyTIR]); in show_status()
2606 printk(" CyMIR %x\n", base_addr[CyMIR]); in show_status()
2607 printk(" CyTPR %x\n", base_addr[CyTPR]); in show_status()
2609 base_addr[CyCAR] = (u_char)channel; in show_status()
2614 printk(" CyRIVR %x\n", base_addr[CyRIVR]); in show_status()
2615 printk(" CyTIVR %x\n", base_addr[CyTIVR]); in show_status()
2616 printk(" CyMIVR %x\n", base_addr[CyMIVR]); in show_status()
2617 printk(" CyMISR %x\n", base_addr[CyMISR]); in show_status()
2622 printk(" CyCCR %x\n", base_addr[CyCCR]); in show_status()
2623 printk(" CyIER %x\n", base_addr[CyIER]); in show_status()
2624 printk(" CyCOR1 %x\n", base_addr[CyCOR1]); in show_status()
2625 printk(" CyCOR2 %x\n", base_addr[CyCOR2]); in show_status()
2626 printk(" CyCOR3 %x\n", base_addr[CyCOR3]); in show_status()
2627 printk(" CyCOR4 %x\n", base_addr[CyCOR4]); in show_status()
2628 printk(" CyCOR5 %x\n", base_addr[CyCOR5]); in show_status()
2630 printk(" CyCCSR %x\n", base_addr[CyCCSR]); in show_status()
2631 printk(" CyRDCR %x\n", base_addr[CyRDCR]); in show_status()
2633 printk(" CySCHR1 %x\n", base_addr[CySCHR1]); in show_status()
2634 printk(" CySCHR2 %x\n", base_addr[CySCHR2]); in show_status()
2636 printk(" CySCHR3 %x\n", base_addr[CySCHR3]); in show_status()
2637 printk(" CySCHR4 %x\n", base_addr[CySCHR4]); in show_status()
2638 printk(" CySCRL %x\n", base_addr[CySCRL]); in show_status()
2639 printk(" CySCRH %x\n", base_addr[CySCRH]); in show_status()
2640 printk(" CyLNC %x\n", base_addr[CyLNC]); in show_status()
2641 printk(" CyMCOR1 %x\n", base_addr[CyMCOR1]); in show_status()
2642 printk(" CyMCOR2 %x\n", base_addr[CyMCOR2]); in show_status()
2644 printk(" CyRTPRL %x\n", base_addr[CyRTPRL]); in show_status()
2645 printk(" CyRTPRH %x\n", base_addr[CyRTPRH]); in show_status()
2646 printk(" CyMSVR1 %x\n", base_addr[CyMSVR1]); in show_status()
2647 printk(" CyMSVR2 %x\n", base_addr[CyMSVR2]); in show_status()
2648 printk(" CyRBPR %x\n", base_addr[CyRBPR]); in show_status()
2649 printk(" CyRCOR %x\n", base_addr[CyRCOR]); in show_status()
2650 printk(" CyTBPR %x\n", base_addr[CyTBPR]); in show_status()
2651 printk(" CyTCOR %x\n", base_addr[CyTCOR]); in show_status()
2745 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in serial167_console_write() local
2758 base_addr[CyCAR] = (u_char)port; in serial167_console_write()
2759 while (base_addr[CyCCR]) in serial167_console_write()
2761 base_addr[CyCCR] = CyENB_XMTR; in serial167_console_write()
2763 ier = base_addr[CyIER]; in serial167_console_write()
2764 base_addr[CyIER] = CyTxMpty; in serial167_console_write()
2771 if ((base_addr[CyLICR] >> 2) == port) { in serial167_console_write()
2774 base_addr[CyTEOIR] = CyNOTRANS; in serial167_console_write()
2778 base_addr[CyTDR] = '\n'; in serial167_console_write()
2784 base_addr[CyTDR] = '\r'; in serial167_console_write()
2788 base_addr[CyTDR] = *str++; in serial167_console_write()
2791 base_addr[CyTEOIR] = 0; in serial167_console_write()
2794 base_addr[CyTEOIR] = CyNOTRANS; in serial167_console_write()
2798 base_addr[CyIER] = ier; in serial167_console_write()
2838 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in putDebugChar() local
2849 base_addr[CyCAR] = (u_char)port; in putDebugChar()
2850 while (base_addr[CyCCR]) in putDebugChar()
2852 base_addr[CyCCR] = CyENB_XMTR; in putDebugChar()
2854 ier = base_addr[CyIER]; in putDebugChar()
2855 base_addr[CyIER] = CyTxMpty; in putDebugChar()
2862 if ((base_addr[CyLICR] >> 2) == port) { in putDebugChar()
2863 base_addr[CyTDR] = c; in putDebugChar()
2864 base_addr[CyTEOIR] = 0; in putDebugChar()
2868 base_addr[CyTEOIR] = CyNOTRANS; in putDebugChar()
2872 base_addr[CyIER] = ier; in putDebugChar()
2879 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in getDebugChar() local
2901 base_addr[CyCAR] = (u_char)port; in getDebugChar()
2903 while (base_addr[CyCCR]) in getDebugChar()
2905 base_addr[CyCCR] = CyENB_RCVR; in getDebugChar()
2907 ier = base_addr[CyIER]; in getDebugChar()
2908 base_addr[CyIER] = CyRxData; in getDebugChar()
2915 if ((base_addr[CyLICR] >> 2) == port) { in getDebugChar()
2916 int cnt = base_addr[CyRFOC]; in getDebugChar()
2919 c = base_addr[CyRDR]; in getDebugChar()
2925 base_addr[CyREOIR] = 0; in getDebugChar()
2936 base_addr[CyREOIR] = CyNOTRANS; in getDebugChar()
2940 base_addr[CyIER] = ier; in getDebugChar()
2963 volatile unsigned char *base_addr = (u_char *)BASE_ADDR; in debug_setup() local
2972 base_addr[CyCAR] = i; in debug_setup()
2973 base_addr[CyLICR] = i << 2; in debug_setup()
2978 base_addr[CyCAR] = DEBUG_PORT; in debug_setup()
2983 base_addr[CyIER] = 0; in debug_setup()
2985 base_addr[CyCMR] = CyASYNC; in debug_setup()
2986 base_addr[CyLICR] = DEBUG_PORT << 2; in debug_setup()
2987 base_addr[CyLIVR] = 0x5c; in debug_setup()
2991 base_addr[CyTCOR] = baud_co[i]; in debug_setup()
2992 base_addr[CyTBPR] = baud_bpr[i]; in debug_setup()
2993 base_addr[CyRCOR] = baud_co[i] >> 5; in debug_setup()
2994 base_addr[CyRBPR] = baud_bpr[i]; in debug_setup()
2998 base_addr[CySCHR1] = 0; in debug_setup()
2999 base_addr[CySCHR2] = 0; in debug_setup()
3000 base_addr[CySCRL] = 0; in debug_setup()
3001 base_addr[CySCRH] = 0; in debug_setup()
3002 base_addr[CyCOR1] = Cy_8_BITS | CyPARITY_NONE; in debug_setup()
3003 base_addr[CyCOR2] = 0; in debug_setup()
3004 base_addr[CyCOR3] = Cy_1_STOP; in debug_setup()
3005 base_addr[CyCOR4] = baud_cor4[i]; in debug_setup()
3006 base_addr[CyCOR5] = 0; in debug_setup()
3007 base_addr[CyCOR6] = 0; in debug_setup()
3008 base_addr[CyCOR7] = 0; in debug_setup()
3010 write_cy_cmd(base_addr,CyINIT_CHAN); in debug_setup()
3011 write_cy_cmd(base_addr,CyENB_RCVR); in debug_setup()
3013 base_addr[CyCAR] = DEBUG_PORT; /* !!! Is this needed? */ in debug_setup()
3015 base_addr[CyRTPRL] = 2; in debug_setup()
3016 base_addr[CyRTPRH] = 0; in debug_setup()
3018 base_addr[CyMSVR1] = CyRTS; in debug_setup()
3019 base_addr[CyMSVR2] = CyDTR; in debug_setup()
3021 base_addr[CyIER] = CyRxData; in debug_setup()