350 #define read_reg(info, reg) inb((info)->io_base + (reg))  macro
357 		 (unsigned char) (read_reg(info, (reg)) | (mask)))  
360 		 (unsigned char) (read_reg(info, (reg)) & ~(mask)))  
924 	while ((status = read_reg(info, (unsigned char)(channel+STAR)) & BIT2)) {  in wait_command_complete()
1090 		if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))  in rx_ready_hdlc()
1098 			data[0] = read_reg(info, CHA + RXFIFO);  in rx_ready_hdlc()
1138 		fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);  in rx_ready_async()
1143 		if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))  in rx_ready_async()
1150 		data   = read_reg(info, CHA + RXFIFO);  in rx_ready_async()
1151 		status = read_reg(info, CHA + RXFIFO);  in rx_ready_async()
1415 	while ((gis = read_reg(info, CHA + GIS))) {  in mgslpc_isr()
1476 			pis = read_reg(info, CHA + PIS);  in mgslpc_isr()
2123 	val = read_reg(info, PVR) & 0x0f;  in set_interface()
3410 		val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;  in mgslpc_set_rate()
3510 	val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);  in loopback_enable()
3514 	val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);  in loopback_enable()
3524 	val = read_reg(info, CHA + MODE) | BIT0;  in loopback_enable()
4088 	if (read_reg(info, CHB + VSTR) & BIT7)  in get_signals()
4090 	if (read_reg(info, CHB + STAR) & BIT1)  in get_signals()
4093 	status = read_reg(info, CHA + PVR);  in get_signals()
4107 	val = read_reg(info, CHA + MODE);  in set_signals()
4246 		if ((read_reg(info, XAD1) != patterns[i]) ||   in register_test()
4247 		    (read_reg(info, XAD2) != patterns[(i + 1) % count])) {  in register_test()