Lines Matching refs:CHB
273 #define CHB 0x40 /* channel B offset */ macro
371 write_reg16(info, CHB + IMR, info->imrb_value); in irq_disable()
381 write_reg16(info, CHB + IMR, info->imrb_value); in irq_enable()
1293 irq_disable(info, CHB, IRQ_CTS); in cts_change()
1330 irq_disable(info, CHB, IRQ_DCD); in dcd_change()
1426 isr = read_reg16(info, CHB + ISR); in mgslpc_isr()
1627 irq_enable(info, CHB, IRQ_DCD | IRQ_CTS); in mgslpc_program_hw()
3439 write_reg(info, CHB + MODE, val); in enable_auxclk()
3451 write_reg(info, CHB + CCR0, 0xc0); in enable_auxclk()
3464 write_reg(info, CHB + CCR1, 0x17); in enable_auxclk()
3479 write_reg(info, CHB + CCR2, 0x38); in enable_auxclk()
3481 write_reg(info, CHB + CCR2, 0x30); in enable_auxclk()
3494 write_reg(info, CHB + CCR4, 0x50); in enable_auxclk()
3500 mgslpc_set_rate(info, CHB, info->params.clock_speed); in enable_auxclk()
3502 mgslpc_set_rate(info, CHB, 921600); in enable_auxclk()
3535 irq_disable(info, CHB, 0xffff); in hdlc_mode()
3736 irq_enable(info, CHB, IRQ_CTS); in hdlc_mode()
3853 write_reg(info, CHB + CCR0, 0x80); in reset_device()
3855 write_reg(info, CHB + MODE, 0); in reset_device()
3859 irq_disable(info, CHB, 0xffff); in reset_device()
3905 irq_disable(info, CHB, 0xffff); in async_mode()
4055 irq_enable(info, CHB, IRQ_CTS); in async_mode()
4088 if (read_reg(info, CHB + VSTR) & BIT7) in get_signals()
4090 if (read_reg(info, CHB + STAR) & BIT1) in get_signals()