414 				      drm_radeon_clear_rect_t *depth_boxes )  in radeon_cp_dispatch_clear()  argument
618 			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );  in radeon_cp_dispatch_clear()
619 			OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );  in radeon_cp_dispatch_clear()
620 			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );  in radeon_cp_dispatch_clear()
622 			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );  in radeon_cp_dispatch_clear()
623 			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );  in radeon_cp_dispatch_clear()
624 			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );  in radeon_cp_dispatch_clear()
626 			OUT_RING( depth_boxes[i].ui[CLEAR_X2] );  in radeon_cp_dispatch_clear()
627 			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );  in radeon_cp_dispatch_clear()
628 			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );  in radeon_cp_dispatch_clear()
692 			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );  in radeon_cp_dispatch_clear()
693 			OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );  in radeon_cp_dispatch_clear()
694 			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );  in radeon_cp_dispatch_clear()
697 			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );  in radeon_cp_dispatch_clear()
698 			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );  in radeon_cp_dispatch_clear()
699 			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );  in radeon_cp_dispatch_clear()
702 			OUT_RING( depth_boxes[i].ui[CLEAR_X2] );  in radeon_cp_dispatch_clear()
703 			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );  in radeon_cp_dispatch_clear()
704 			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );  in radeon_cp_dispatch_clear()
1274 	drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];  in radeon_cp_clear()  local
1288 	if ( copy_from_user( &depth_boxes, clear.depth_boxes,  in radeon_cp_clear()
1289 			     sarea_priv->nbox * sizeof(depth_boxes[0]) ) )  in radeon_cp_clear()
1292 	radeon_cp_dispatch_clear( dev, &clear, depth_boxes );  in radeon_cp_clear()