381 static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) {  in rd_regw()  function
428   while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & FLUSH_CHANNEL)  in WAIT_FLUSH_RX_COMPLETE()
439   while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & RX_CHANNEL_UPDATE_IN_PROGRESS)  in WAIT_UPDATE_COMPLETE()
463     return rd_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF);  in query_tx_channel_config()
488   PRINTD (DBG_REGS, "RX CONFIG: %#x", rd_regw (dev, RX_CONFIG_OFF));
489   PRINTD (DBG_REGS, "TX CONFIG: %#x", rd_regw (dev, TX_CONFIG_OFF));
490   PRINTD (DBG_REGS, "TX STATUS: %#x", rd_regw (dev, TX_STATUS_OFF));
928     rx_q_entry * wr_ptr = &memmap->rx_q_entries[rd_regw (dev, RX_QUEUE_WR_PTR_OFF)];  in hrz_close_rx()
1284   wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);  in rx_disabled_handler()
1492       dev->tx_cell_count += rd_regw (dev, TX_CELL_COUNT_OFF);  in do_housekeeping()
1493       dev->rx_cell_count += rd_regw (dev, RX_CELL_COUNT_OFF);  in do_housekeeping()
1494       dev->hec_error_count += rd_regw (dev, HEC_ERROR_COUNT_OFF);  in do_housekeeping()
1495       dev->unassigned_cell_count += rd_regw (dev, UNASSIGNED_CELL_COUNT_OFF);  in do_housekeeping()
1515   while (!(idle_channels = rd_regw (dev, TX_STATUS_OFF) & IDLE_CHANNELS_MASK)) {  in setup_idle_tx_channel()
1716   while ((free_buffers = rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF)) < buffers_required) {  in hrz_send()
2018   wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);  in hrz_init()
2734 		    rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF),  in hrz_proc_read()
2735 		    rd_regw (dev, RX_FREE_BUFFER_COUNT_OFF),  in hrz_proc_read()