Lines Matching refs:he_writel
172 #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0) macro
181 he_writel(he_dev, val, CON_DAT); in he_writel_internal()
183 he_writel(he_dev, flags | CON_CTL_WRITE | CON_CTL_ADDR(addr), CON_CTL); in he_writel_internal()
199 he_writel(he_dev, flags | CON_CTL_READ | CON_CTL_ADDR(addr), CON_CTL); in he_readl_internal()
453 he_writel(he_dev, lbufd_index, RLBF0_H); in he_init_rx_lbfp0()
469 he_writel(he_dev, lbufd_index - 2, RLBF0_T); in he_init_rx_lbfp0()
470 he_writel(he_dev, he_dev->r0_numbuffs, RLBF0_C); in he_init_rx_lbfp0()
484 he_writel(he_dev, lbufd_index, RLBF1_H); in he_init_rx_lbfp1()
500 he_writel(he_dev, lbufd_index - 2, RLBF1_T); in he_init_rx_lbfp1()
501 he_writel(he_dev, he_dev->r1_numbuffs, RLBF1_C); in he_init_rx_lbfp1()
515 he_writel(he_dev, lbufd_index, TLBF_H); in he_init_tx_lbfp()
531 he_writel(he_dev, lbufd_index - 1, TLBF_T); in he_init_tx_lbfp()
549 he_writel(he_dev, he_dev->tpdrq_phys, TPDRQ_B_H); in he_init_tpdrq()
550 he_writel(he_dev, 0, TPDRQ_T); in he_init_tpdrq()
551 he_writel(he_dev, CONFIG_TPDRQ_SIZE - 1, TPDRQ_S); in he_init_tpdrq()
825 he_writel(he_dev, he_dev->rbps_phys, G0_RBPS_S + (group * 32)); in he_init_group()
826 he_writel(he_dev, RBPS_MASK(he_dev->rbps_tail), in he_init_group()
828 he_writel(he_dev, CONFIG_RBPS_BUFSIZE/4, in he_init_group()
830 he_writel(he_dev, in he_init_group()
836 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32)); in he_init_group()
837 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32)); in he_init_group()
838 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32)); in he_init_group()
839 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0), in he_init_group()
888 he_writel(he_dev, he_dev->rbpl_phys, G0_RBPL_S + (group * 32)); in he_init_group()
889 he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), in he_init_group()
891 he_writel(he_dev, CONFIG_RBPL_BUFSIZE/4, in he_init_group()
893 he_writel(he_dev, in he_init_group()
910 he_writel(he_dev, he_dev->rbrq_phys, G0_RBRQ_ST + (group * 16)); in he_init_group()
911 he_writel(he_dev, 0, G0_RBRQ_H + (group * 16)); in he_init_group()
912 he_writel(he_dev, in he_init_group()
917 he_writel(he_dev, RBRQ_TIME(768) | RBRQ_COUNT(7), in he_init_group()
920 he_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1), in he_init_group()
935 he_writel(he_dev, he_dev->tbrq_phys, G0_TBRQ_B_T + (group * 16)); in he_init_group()
936 he_writel(he_dev, 0, G0_TBRQ_H + (group * 16)); in he_init_group()
937 he_writel(he_dev, CONFIG_TBRQ_SIZE - 1, G0_TBRQ_S + (group * 16)); in he_init_group()
938 he_writel(he_dev, CONFIG_TBRQ_THRESH, G0_TBRQ_THRESH + (group * 16)); in he_init_group()
966 he_writel(he_dev, he_dev->irq_phys, IRQ0_BASE); in he_init_irq()
967 he_writel(he_dev, in he_init_irq()
970 he_writel(he_dev, IRQ_INT_A | IRQ_TYPE_LINE, IRQ0_CNTL); in he_init_irq()
971 he_writel(he_dev, 0x0, IRQ0_DATA); in he_init_irq()
973 he_writel(he_dev, 0x0, IRQ1_BASE); in he_init_irq()
974 he_writel(he_dev, 0x0, IRQ1_HEAD); in he_init_irq()
975 he_writel(he_dev, 0x0, IRQ1_CNTL); in he_init_irq()
976 he_writel(he_dev, 0x0, IRQ1_DATA); in he_init_irq()
978 he_writel(he_dev, 0x0, IRQ2_BASE); in he_init_irq()
979 he_writel(he_dev, 0x0, IRQ2_HEAD); in he_init_irq()
980 he_writel(he_dev, 0x0, IRQ2_CNTL); in he_init_irq()
981 he_writel(he_dev, 0x0, IRQ2_DATA); in he_init_irq()
983 he_writel(he_dev, 0x0, IRQ3_BASE); in he_init_irq()
984 he_writel(he_dev, 0x0, IRQ3_HEAD); in he_init_irq()
985 he_writel(he_dev, 0x0, IRQ3_CNTL); in he_init_irq()
986 he_writel(he_dev, 0x0, IRQ3_DATA); in he_init_irq()
990 he_writel(he_dev, 0x0, GRP_10_MAP); in he_init_irq()
991 he_writel(he_dev, 0x0, GRP_32_MAP); in he_init_irq()
992 he_writel(he_dev, 0x0, GRP_54_MAP); in he_init_irq()
993 he_writel(he_dev, 0x0, GRP_76_MAP); in he_init_irq()
1089 he_writel(he_dev, 0x0, RESET_CNTL); in he_start()
1090 he_writel(he_dev, 0xff, RESET_CNTL); in he_start()
1149 he_writel(he_dev, lb_swap, LB_SWAP); in he_start()
1152 he_writel(he_dev, he_is622(he_dev) ? LB_64_ENB : 0x0, SDRAM_CTL); in he_start()
1156 he_writel(he_dev, lb_swap, LB_SWAP); in he_start()
1170 he_writel(he_dev, host_cntl, HOST_CNTL); in he_start()
1268 he_writel(he_dev, in he_start()
1275 he_writel(he_dev, BANK_ON | in he_start()
1279 he_writel(he_dev, in he_start()
1282 he_writel(he_dev, in he_start()
1286 he_writel(he_dev, he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD, LB_CONFIG); in he_start()
1288 he_writel(he_dev, in he_start()
1294 he_writel(he_dev, DRF_THRESH(0x20) | in he_start()
1299 he_writel(he_dev, 0x0, TXAAL5_PROTO); in he_start()
1301 he_writel(he_dev, PHY_INT_ENB | in he_start()
1344 he_writel(he_dev, CONFIG_TSRB, TSRB_BA); in he_start()
1345 he_writel(he_dev, CONFIG_TSRC, TSRC_BA); in he_start()
1346 he_writel(he_dev, CONFIG_TSRD, TSRD_BA); in he_start()
1347 he_writel(he_dev, CONFIG_TMABR, TMABR_BA); in he_start()
1348 he_writel(he_dev, CONFIG_TPDBA, TPD_BA); in he_start()
1378 he_writel(he_dev, 0x08000, RCMLBM_BA); in he_start()
1379 he_writel(he_dev, 0x0e000, RCMRSRB_BA); in he_start()
1380 he_writel(he_dev, 0x0d800, RCMABR_BA); in he_start()
1387 he_writel(he_dev, 0x0, RLBC_H); in he_start()
1388 he_writel(he_dev, 0x0, RLBC_T); in he_start()
1389 he_writel(he_dev, 0x0, RLBC_H2); in he_start()
1391 he_writel(he_dev, 512, RXTHRSH); /* 10% of r0+r1 buffers */ in he_start()
1392 he_writel(he_dev, 256, LITHRSH); /* 5% of r0+r1 buffers */ in he_start()
1396 he_writel(he_dev, he_is622(he_dev) ? 0x104780 : 0x800, UBUFF_BA); in he_start()
1401 he_writel(he_dev, 0x000f, G0_INMQ_S); in he_start()
1402 he_writel(he_dev, 0x200f, G0_INMQ_L); in he_start()
1404 he_writel(he_dev, 0x001f, G1_INMQ_S); in he_start()
1405 he_writel(he_dev, 0x201f, G1_INMQ_L); in he_start()
1407 he_writel(he_dev, 0x002f, G2_INMQ_S); in he_start()
1408 he_writel(he_dev, 0x202f, G2_INMQ_L); in he_start()
1410 he_writel(he_dev, 0x003f, G3_INMQ_S); in he_start()
1411 he_writel(he_dev, 0x203f, G3_INMQ_L); in he_start()
1413 he_writel(he_dev, 0x004f, G4_INMQ_S); in he_start()
1414 he_writel(he_dev, 0x204f, G4_INMQ_L); in he_start()
1416 he_writel(he_dev, 0x005f, G5_INMQ_S); in he_start()
1417 he_writel(he_dev, 0x205f, G5_INMQ_L); in he_start()
1419 he_writel(he_dev, 0x006f, G6_INMQ_S); in he_start()
1420 he_writel(he_dev, 0x206f, G6_INMQ_L); in he_start()
1422 he_writel(he_dev, 0x007f, G7_INMQ_S); in he_start()
1423 he_writel(he_dev, 0x207f, G7_INMQ_L); in he_start()
1425 he_writel(he_dev, 0x0000, G0_INMQ_S); in he_start()
1426 he_writel(he_dev, 0x0008, G0_INMQ_L); in he_start()
1428 he_writel(he_dev, 0x0001, G1_INMQ_S); in he_start()
1429 he_writel(he_dev, 0x0009, G1_INMQ_L); in he_start()
1431 he_writel(he_dev, 0x0002, G2_INMQ_S); in he_start()
1432 he_writel(he_dev, 0x000a, G2_INMQ_L); in he_start()
1434 he_writel(he_dev, 0x0003, G3_INMQ_S); in he_start()
1435 he_writel(he_dev, 0x000b, G3_INMQ_L); in he_start()
1437 he_writel(he_dev, 0x0004, G4_INMQ_S); in he_start()
1438 he_writel(he_dev, 0x000c, G4_INMQ_L); in he_start()
1440 he_writel(he_dev, 0x0005, G5_INMQ_S); in he_start()
1441 he_writel(he_dev, 0x000d, G5_INMQ_L); in he_start()
1443 he_writel(he_dev, 0x0006, G6_INMQ_S); in he_start()
1444 he_writel(he_dev, 0x000e, G6_INMQ_L); in he_start()
1446 he_writel(he_dev, 0x0007, G7_INMQ_S); in he_start()
1447 he_writel(he_dev, 0x000f, G7_INMQ_L); in he_start()
1452 he_writel(he_dev, 0x0, MCC); in he_start()
1453 he_writel(he_dev, 0x0, OEC); in he_start()
1454 he_writel(he_dev, 0x0, DCC); in he_start()
1455 he_writel(he_dev, 0x0, CEC); in he_start()
1498 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32)); in he_start()
1499 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32)); in he_start()
1500 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32)); in he_start()
1501 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0), in he_start()
1504 he_writel(he_dev, 0x0, G0_RBPL_S + (group * 32)); in he_start()
1505 he_writel(he_dev, 0x0, G0_RBPL_T + (group * 32)); in he_start()
1506 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0), in he_start()
1508 he_writel(he_dev, 0x0, G0_RBPL_BS + (group * 32)); in he_start()
1510 he_writel(he_dev, 0x0, G0_RBRQ_ST + (group * 16)); in he_start()
1511 he_writel(he_dev, 0x0, G0_RBRQ_H + (group * 16)); in he_start()
1512 he_writel(he_dev, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0), in he_start()
1514 he_writel(he_dev, 0x0, G0_RBRQ_I + (group * 16)); in he_start()
1516 he_writel(he_dev, 0x0, G0_TBRQ_B_T + (group * 16)); in he_start()
1517 he_writel(he_dev, 0x0, G0_TBRQ_H + (group * 16)); in he_start()
1518 he_writel(he_dev, TBRQ_THRESH(0x1), in he_start()
1520 he_writel(he_dev, 0x0, G0_TBRQ_S + (group * 16)); in he_start()
1532 he_writel(he_dev, he_dev->hsp_phys, HSP_BA); in he_start()
1560 he_writel(he_dev, reg, RC_CONFIG); in he_start()
1612 he_writel(he_dev, reg, RC_CONFIG); in he_stop()
1950 he_writel(he_dev, RBRQ_MASK(he_dev->rbrq_head), in he_service_rbrq()
2043 he_writel(he_dev, TBRQ_MASK(he_dev->tbrq_head), in he_service_tbrq()
2073 he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), G0_RBPL_T); in he_service_rbpl()
2101 he_writel(he_dev, RBPS_MASK(he_dev->rbps_tail), G0_RBPS_T); in he_service_rbps()
2194 he_writel(he_dev, in he_tasklet()
2239 he_writel(he_dev, INT_CLEAR_A, INT_FIFO); /* clear interrupt */ in he_irq_handler()
2308 he_writel(he_dev, TPDRQ_MASK(he_dev->tpdrq_tail), TPDRQ_T); in __enqueue_tpd()
2895 he_writel(he_dev, val, FRAMER + (addr*4)); in he_phy_put()
3013 he_writel(he_dev, val, HOST_CNTL); in read_prom_byte()
3017 he_writel(he_dev, val | readtab[i], HOST_CNTL); in read_prom_byte()
3023 he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL); in read_prom_byte()
3025 he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL); in read_prom_byte()
3032 he_writel(he_dev, val, HOST_CNTL); in read_prom_byte()
3036 he_writel(he_dev, val | clocktab[j++], HOST_CNTL); in read_prom_byte()
3041 he_writel(he_dev, val | clocktab[j++], HOST_CNTL); in read_prom_byte()
3045 he_writel(he_dev, val | ID_CS, HOST_CNTL); in read_prom_byte()