Lines Matching refs:g0
74 wrpr %g0, 1, %tl ! Behave as if we are at TL0
92 stxa %g5, [%g0] ASI_ITLB_DATA_IN ! put into tlb
110 stxa %g5, [%g0] ASI_DTLB_DATA_IN ! put into tlb
133 stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
141 andcc %g5, %g4, %g0
145 andcc %g5, FPRS_FEF, %g0
153 add %g0, %g0, %g0
157 wr %g0, FPRS_FEF, %fprs ! LSU Group+4bubbles
158 andcc %g5, FPRS_FEF, %g0 ! IEU1 Group
162 1: andcc %g5, FPRS_DL, %g0 ! IEU1
165 andcc %g5, FPRS_DU, %g0 ! IEU1 Group
204 stxa %g0, [%g3] ASI_DMMU
222 2: andcc %g5, FPRS_DU, %g0
229 stxa %g0, [%g3] ASI_DMMU
254 stxa %g0, [%g3] ASI_DMMU
271 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
292 andcc %g3, TSTATE_PRIV, %g0
301 andcc %g3, %g1, %g0
320 jmpl %g1 + %g2, %g0
363 jmpl %g1 + %g2, %g0
418 stxa %g0, [%g3] ASI_DMMU
420 andcc %g1, FPRS_DL, %g0
425 andcc %g1, FPRS_DU, %g0
435 wr %g0, 0, %fprs
455 ldxa [%g3 + %g0] ASI_INTR_R, %g3
460 stxa %g0, [%g0] ASI_INTR_RECEIVE
482 ldxa [%g1 + %g0] ASI_INTR_R, %g1
485 ldxa [%g7 + %g0] ASI_INTR_R, %g7
486 stxa %g0, [%g0] ASI_INTR_RECEIVE
492 1: jmpl %g3, %g0
513 stx %g0, [%o0 + 0x00]
522 stx %g0, [%o0 + 0x40]
531 stx %g0, [%o0 + 0x80]
548 ldx [%o0 + 0x00], %g0
557 ldx [%o0 + 0x40], %g0
566 ldx [%o0 + 0x80], %g0
588 or %g0, %ulo(TSTATE_ICC), %o3
618 wr %g0, (1 << 11), %clear_softint
631 andcc %g7, 0x80, %g0
633 andcc %g7, 0x20, %g0
635 andcc %g7, 0x40, %g0
642 orcc %g0, %g5, %g0
652 orcc %g0, %g5, %g0
679 st %g0, [%g1 + %lo(doing_pdma)]
696 stwa %g0, [%g4] ASI_PHYS_BYPASS_EC_E ! ICLR_IDLE
706 st %g0, [%g1 + %lo(doing_pdma)]
710 wrpr %g0, 15, %pil
743 stxa %g0, [%g0] ASI_ESTATE_ERROR_EN
747 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
754 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
781 1: ldxa [%g0] ASI_UDBH_ERROR_R, %g3
788 stxa %g3, [%g0] ASI_UDB_ERROR_W
806 stxa %g4, [%g0] ASI_AFSR
813 wrpr %g0, 15, %pil
860 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
863 andcc %g4, %g3, %g0 ! Check for UE
872 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g3
874 stxa %g3, [%g0] ASI_ESTATE_ERROR_EN
890 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
917 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
937 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
955 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
984 ldxa [%g0] ASI_SAFARI_CONFIG, %g2; \
988 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2; \
1090 ldxa [%g2] ASI_EC_R, %g0; \
1106 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1108 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1111 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
1115 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1117 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1120 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
1125 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1127 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1130 jmpl %g2 + %lo(cheetah_cee), %g0
1134 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1136 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1139 jmpl %g2 + %lo(cheetah_cee), %g0
1144 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
1146 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
1149 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
1153 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
1155 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
1158 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
1172 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
1192 jmpl %g3 + %lo(do_dcpe_tl1), %g0
1202 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
1222 jmpl %g3 + %lo(do_icpe_tl1), %g0
1240 andcc %g4, %g3, %g0 ! Interrupt globals in use?
1259 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
1286 andcc %g4, %g3, %g0 ! Interrupt globals in use?
1300 stxa %g0, [%g3] ASI_IC_TAG
1325 1: stxa %g0, [%g1] ASI_DCACHE_TAG
1330 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1332 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1350 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1352 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1356 ldxa [%g0] ASI_AFSR, %g4
1357 ldxa [%g0] ASI_AFAR, %g5
1358 stxa %g4, [%g0] ASI_AFSR
1364 wrpr %g0, 15, %pil
1376 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1378 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1382 ldxa [%g0] ASI_AFSR, %g4
1383 ldxa [%g0] ASI_AFAR, %g5
1384 stxa %g4, [%g0] ASI_AFSR
1390 wrpr %g0, 15, %pil
1402 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1404 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1408 ldxa [%g0] ASI_AFSR, %g4
1409 ldxa [%g0] ASI_AFAR, %g5
1410 stxa %g4, [%g0] ASI_AFSR
1416 wrpr %g0, 15, %pil
1428 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1450 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1470 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1488 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1574 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1580 jmpl %g1, %g0
1647 andcc %l5, 0x02, %g0
1701 andcc %l0, SPARC_FLAG_PERFCTR, %g0
1705 wr %g0, %o7, %pcr
1714 99: wr %g0, %g0, %pic
1715 rd %pic, %g0
1719 sparc_exit: wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV), %pstate
1724 wrpr %g0, 0x0, %otherwin
1725 wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE), %pstate
1727 stb %g0, [%g6 + AOFF_task_thread + AOFF_thread_w_saved]
1776 andcc %l0, 0x02, %g0 ! IEU0 Group
1804 andcc %l0, 0x02, %g0 ! IEU1 Group+1 bubble
1841 andcc %l0, SPARC_FLAG_SYS_SUCCESS, %g0
1843 andcc %l6, 0x02, %g0
1852 sub %g0, %o0, %o0
1882 restore %g0, %g0, %g0