191 unsigned int pcic_regs;  variable
349 	pcic->pcic_regs = (unsigned long)  in pcic_probe()
351 	if (!pcic->pcic_regs) {  in pcic_probe()
397 		pcic_regs = pcic->pcic_regs;  in pcic_probe()
454 	       pcic->pcic_regs+PCI_DVMA_CONTROL);  in pcibios_init()
461 	writel(0xF0000000UL, pcic->pcic_regs+PCI_SIZE_0);  in pcibios_init()
463 	       pcic->pcic_regs+PCI_BASE_ADDRESS_0);  in pcibios_init()
597 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);  in pcic_fill_irq()
600 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);  in pcic_fill_irq()
621 			ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);  in pcic_fill_irq()
624 			writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_HI);  in pcic_fill_irq()
626 			ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);  in pcic_fill_irq()
629 			writew(ivec, pcic->pcic_regs+PCI_INT_SELECT_LO);  in pcic_fill_irq()
726 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_LO);  in pcic_pin_to_irq()
729 		ivec = readw(pcic->pcic_regs+PCI_INT_SELECT_HI);  in pcic_pin_to_irq()
744 	pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);  in pcic_clear_clock_irq()
771 	writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);  in pci_time_init()
773 	v = readb(pcic->pcic_regs+PCI_COUNTER_IRQ);  in pci_time_init()
776 		pcic->pcic_regs+PCI_COUNTER_IRQ);  in pci_time_init()
796 	    readl(pcic0.pcic_regs+PCI_SYS_COUNTER) & ~PCI_SYS_COUNTER_OVERFLOW;  in do_gettimeoffset()
849 	writeb(0, pcic->pcic_regs+PCI_SYS_STATUS);
919 	writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);  in pcic_disable_irq()
929 	writel(mask, pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);  in pcic_enable_irq()
948 	writel(get_irqmask(pil), pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_SET);  in pcic_disable_pil_irq()
953 	writel(get_irqmask(pil), pcic0.pcic_regs+PCI_SYS_INT_TARGET_MASK_CLEAR);  in pcic_enable_pil_irq()