56 #define v320usc_outl(value, addr)	writel(value, reg32(addr))  macro
66 	v320usc_outl(  in set_io_cycles()
83 	v320usc_outl((tempscratch &   in set_config_cycles()
413 	v320usc_outl(0x10120001, LB_BUS_CFG);  in pcibios_init()
424 	v320usc_outl(0x00008800, PCI_HDR_CFG);  in pcibios_init()
426 	v320usc_outl(0x00005761, DRAM_BLK0);  in pcibios_init()
427 	v320usc_outl(0x02005761, DRAM_BLK1);  in pcibios_init()
428 	v320usc_outl(0x00000000, DRAM_BLK2);  in pcibios_init()
429 	v320usc_outl(0x00000000, DRAM_BLK3);  in pcibios_init()
430 	v320usc_outl(0x00000942, DRAM_CFG);  in pcibios_init()
431 	v320usc_outl(0x80030066, PCI_BUS_CFG);  in pcibios_init()
433 	v320usc_outl(v320usc_inl(INT_STAT), INT_STAT); /* clear any ints */  in pcibios_init()
435 	v320usc_outl(0x00000000, INT_CFG0);  in pcibios_init()
436 	v320usc_outl(0x00000000, INT_CFG1);  in pcibios_init()
437 	v320usc_outl(0x00000000, INT_CFG2);  in pcibios_init()
438 	v320usc_outl(0x00000000, INT_CFG3);  in pcibios_init()
441 	v320usc_outl(0x0c000000, PCI_I2O_BASE);  in pcibios_init()
442 	v320usc_outl(0x0c010053, PCI_I2O_MAP);  in pcibios_init()
444 	v320usc_outl(0x0c000001, PCI_MEM_BASE);  in pcibios_init()
445 	v320usc_outl(0x00010063, PCI_MEM_MAP);  in pcibios_init()
447 	v320usc_outl(0x00000000, LB_PCU_BASE); /* Disable PCU on SuperH */  in pcibios_init()
449 	v320usc_outl(0x00000081, PCI_PCU_BASE);  in pcibios_init()
453 	v320usc_outl(0xB4002030, LB_PCI_BASE0); /* 64Mb */  in pcibios_init()
454 	v320usc_outl(0xACB86030, LB_PCI_BASE1); /* 64Mb */  in pcibios_init()
456 	v320usc_outl(0x9e002010, LB_PCI_BASE0); /* 16Mb */  in pcibios_init()
457 	v320usc_outl(0x9fAb6010, LB_PCI_BASE1); /* 16Mb */  in pcibios_init()
468 	v320usc_outl(0xB4002030, LB_PCI_BASE0); /* 64Mb */  in pcibios_init()
469 	v320usc_outl(0xACB86030, LB_PCI_BASE1); /* 64Mb */  in pcibios_init()
471 	v320usc_outl(0x9e002010, LB_PCI_BASE0); /* 16Mb */  in pcibios_init()
472 	v320usc_outl(0x9fAb6010, LB_PCI_BASE1); /* 16Mb */  in pcibios_init()