Lines Matching refs:r21
136 mtspr SPRG1,r21; \
138 mfspr r21,SPRG2; /* exception stack to use from */ \
139 cmpwi 0,r21,0; /* user mode or RTAS */ \
141 tophys(r21,r1); /* use tophys(kernel sp) otherwise */ \
142 subi r21,r21,INT_FRAME_SIZE; /* alloc exc. frame */\
143 1: stw r20,_CCR(r21); /* save registers */ \
144 stw r22,GPR22(r21); \
145 stw r23,GPR23(r21); \
147 stw r20,GPR20(r21); \
149 stw r22,GPR21(r21); \
151 stw r20,_LINK(r21); \
153 stw r22,_CTR(r21); \
155 stw r20,_XER(r21); \
158 stw r0,GPR0(r21); \
159 stw r1,GPR1(r21); \
160 stw r2,GPR2(r21); \
161 stw r1,0(r21); \
162 tovirt(r1,r21); /* set new kernel sp */ \
163 SAVE_4GPRS(3, r21); \
164 SAVE_GPR(7, r21);
201 stw r20,_DSISR(r21)
204 stw r4,_DAR(r21)
242 stw r4,_DAR(r21)
244 stw r5,_DSISR(r21)
281 stw r3,ORIG_GPR3(r21)
320 stw r21, 4(r0)
333 andi. r21, r20, 0x0800 /* Address >= 0x80000000 */
335 lis r21, swapper_pg_dir@h
336 ori r21, r21, swapper_pg_dir@l
337 rlwimi r20, r21, 0, 2, 19
339 lwz r21, 0(r20) /* Get the level 1 entry */
340 rlwinm. r20, r21,0,0,19 /* Extract page descriptor page address */
345 tophys(r21,r21)
346 ori r21,r21,1 /* Set valid bit */
353 mtspr MI_TWC, r21 /* Set segment attributes */
359 mtspr MD_TWC, r21 /* Load pte table base address */
360 mfspr r21, MD_TWC /* ....and get the pte address */
361 lwz r20, 0(r21) /* Get the pte */
364 stw r20, 0(r21)
372 2: li r21, 0x00f0
373 rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
383 lwz r21, 0(r0)
384 mtcr r21
385 lwz r21, 4(r0)
402 stw r21, 4(r0)
408 andi. r21, r20, 0x0800
410 lis r21, swapper_pg_dir@h
411 ori r21, r21, swapper_pg_dir@l
412 rlwimi r20, r21, 0, 2, 19
414 lwz r21, 0(r20) /* Get the level 1 entry */
415 rlwinm. r20, r21,0,0,19 /* Extract page descriptor page address */
419 tophys(r21, r21)
420 ori r21, r21, 1 /* Set valid bit in physical L2 page */
427 mtspr MD_TWC, r21 /* Load pte table base address */
437 rlwimi r21, r20, 0, 27, 27
443 mtspr MD_TWC, r21
445 mfspr r21, MD_TWC /* get the pte address again */
447 stw r20, 0(r21)
455 2: li r21, 0x00f0
456 rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
466 lwz r21, 0(r0)
467 mtcr r21
468 lwz r21, 4(r0)
501 stw r21, 4(r0)
506 andis. r21, r20, 0x0200 /* If set, indicates store op */
526 rlwinm r21, r20, 0, 0, 19
527 ori r21, r21, MD_EVALID
529 rlwimi r21, r20, 0, 28, 31
535 mtspr MD_EPN, r21
542 andi. r21, r20, 0x0800
544 lis r21, swapper_pg_dir@h
545 ori r21, r21, swapper_pg_dir@l
546 rlwimi r20, r21, 0, 2, 19
548 lwz r21, 0(r20) /* Get the level 1 entry */
549 rlwinm. r20, r21,0,0,19 /* Extract page descriptor page address */
554 tophys(r21, r21)
555 ori r21, r21, 1 /* Set valid bit in physical L2 page */
561 mtspr MD_TWC, r21 /* Load pte table base address */
562 mfspr r21, MD_TWC /* ....and get the pte address */
563 lwz r20, 0(r21) /* Get the pte */
565 andi. r21, r20, _PAGE_RW /* Is it writeable? */
571 mfspr r21, MD_TWC /* Get pte address again */
572 stw r20, 0(r21) /* and update pte in table */
580 li r21, 0x00f0
581 rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
591 lwz r21, 0(r0)
592 mtcr r21
593 lwz r21, 4(r0)
600 lwz r21, 0(r0)
601 mtcr r21
602 lwz r21, 4(r0)
634 stw r22,_NIP(r21)
637 stw r23,_MSR(r21)
638 SAVE_4GPRS(8, r21)
639 SAVE_8GPRS(12, r21)
640 SAVE_8GPRS(24, r21)
650 stw r24,TRAP(r21)
652 stw r22,RESULT(r21)