317 	       r4030_read_reg32(JAZZ_R4030_CONFIG));  in vdma_stats()
319 	       r4030_read_reg32(JAZZ_R4030_TRSTBL_BASE));  in vdma_stats()
321 	       r4030_read_reg32(JAZZ_R4030_TRSTBL_LIM));  in vdma_stats()
323 	       r4030_read_reg32(JAZZ_R4030_INV_ADDR));  in vdma_stats()
325 	       r4030_read_reg32(JAZZ_R4030_R_FAIL_ADDR));  in vdma_stats()
327 	       r4030_read_reg32(JAZZ_R4030_M_FAIL_ADDR));  in vdma_stats()
329 	       r4030_read_reg32(JAZZ_R4030_IRQ_SOURCE));  in vdma_stats()
331 	       r4030_read_reg32(JAZZ_R4030_I386_ERROR));  in vdma_stats()
335 		       (unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_MODE +  in vdma_stats()
340 		printk("%04x ", r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +  in vdma_stats()
362 	status = r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5));  in vdma_enable()
372 			  r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +  in vdma_enable()
380 			  r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +  in vdma_enable()
391 		int status = r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +  in vdma_disable()
399 		       (unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_MODE +  in vdma_disable()
401 		       (unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_ADDR +  in vdma_disable()
403 		       (unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_COUNT +  in vdma_disable()
408 			  r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +  in vdma_disable()
467 				  r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +  in vdma_set_mode()
474 				  r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +  in vdma_set_mode()
518 	    r4030_read_reg32(JAZZ_R4030_CHNL_COUNT + (channel << 5));  in vdma_get_residue()
534 	enable = r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5));  in vdma_get_enable()