Lines Matching refs:ddb_set_pdar
214 ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0); in ddb5476_board_init()
215 ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0); in ddb5476_board_init()
216 ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0); in ddb5476_board_init()
217 ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0); in ddb5476_board_init()
220 ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0); in ddb5476_board_init()
221 ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0); in ddb5476_board_init()
222 ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0); in ddb5476_board_init()
235 ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1); in ddb5476_board_init()
238 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1); in ddb5476_board_init()
261 ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1); in ddb5476_board_init()
331 ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1); in ddb5476_board_init()