Lines Matching refs:dev
27 static void qube_expansion_slot_bist(struct pci_dev *dev) in qube_expansion_slot_bist() argument
32 pci_read_config_byte(dev, PCI_BIST, &ctrl); in qube_expansion_slot_bist()
36 pci_write_config_byte(dev, PCI_BIST, ctrl|PCI_BIST_START); in qube_expansion_slot_bist()
38 pci_read_config_byte(dev, PCI_BIST, &ctrl); in qube_expansion_slot_bist()
47 static void qube_expansion_slot_fixup(struct pci_dev *dev) in qube_expansion_slot_fixup() argument
55 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); in qube_expansion_slot_fixup()
57 pci_write_config_word(dev, PCI_COMMAND, pci_cmd); in qube_expansion_slot_fixup()
60 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_QUBE_SLOT_IRQ); in qube_expansion_slot_fixup()
61 dev->irq = COBALT_QUBE_SLOT_IRQ; in qube_expansion_slot_fixup()
63 ioaddr_base += 0x2000 * PCI_FUNC(dev->devfn); in qube_expansion_slot_fixup()
64 memaddr_base += 0x2000 * PCI_FUNC(dev->devfn); in qube_expansion_slot_fixup()
73 pci_read_config_dword(dev, regaddr, &rval); in qube_expansion_slot_fixup()
79 pci_write_config_dword(dev, regaddr, 0xffffffff); in qube_expansion_slot_fixup()
80 pci_read_config_dword(dev, regaddr, &rval); in qube_expansion_slot_fixup()
94 pci_write_config_dword(dev, regaddr, rval | aspace); in qube_expansion_slot_fixup()
95 dev->resource[i].start = rval; in qube_expansion_slot_fixup()
96 dev->resource[i].end = *basep - 1; in qube_expansion_slot_fixup()
98 dev->resource[i].start -= 0x10000000; in qube_expansion_slot_fixup()
99 dev->resource[i].end -= 0x10000000; in qube_expansion_slot_fixup()
102 qube_expansion_slot_bist(dev); in qube_expansion_slot_fixup()
105 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) in qube_raq_via_bmIDE_fixup() argument
111 pci_read_config_word(dev, PCI_COMMAND, &cfgword); in qube_raq_via_bmIDE_fixup()
113 pci_write_config_word(dev, PCI_COMMAND, cfgword); in qube_raq_via_bmIDE_fixup()
116 pci_write_config_byte(dev, 0x40, 0xb); in qube_raq_via_bmIDE_fixup()
119 pci_read_config_byte(dev, PCI_LATENCY_TIMER, <); in qube_raq_via_bmIDE_fixup()
121 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); in qube_raq_via_bmIDE_fixup()
122 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); in qube_raq_via_bmIDE_fixup()
125 static void qube_raq_tulip_fixup(struct pci_dev *dev) in qube_raq_tulip_fixup() argument
130 if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH0) { in qube_raq_tulip_fixup()
132 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, in qube_raq_tulip_fixup()
134 dev->irq = COBALT_ETH0_IRQ; in qube_raq_tulip_fixup()
136 dev->resource[0].start = 0x100000; in qube_raq_tulip_fixup()
137 dev->resource[0].end = 0x10007f; in qube_raq_tulip_fixup()
139 dev->resource[1].start = 0x12000000; in qube_raq_tulip_fixup()
140 dev->resource[1].end = dev->resource[1].start + 0x3ff; in qube_raq_tulip_fixup()
141 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, dev->resource[1].start); in qube_raq_tulip_fixup()
144 } else if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_ETH1) { in qube_raq_tulip_fixup()
147 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); in qube_raq_tulip_fixup()
149 pci_write_config_word(dev, PCI_COMMAND, pci_cmd); in qube_raq_tulip_fixup()
152 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, in qube_raq_tulip_fixup()
154 dev->irq = COBALT_ETH1_IRQ; in qube_raq_tulip_fixup()
159 dev->resource[0].start = 0x101000; in qube_raq_tulip_fixup()
160 dev->resource[0].end = 0x10107f; in qube_raq_tulip_fixup()
162 dev->resource[1].start = 0x12000400; in qube_raq_tulip_fixup()
163 dev->resource[1].end = dev->resource[1].start + 0x3ff; in qube_raq_tulip_fixup()
164 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, dev->resource[1].start); in qube_raq_tulip_fixup()
168 static void qube_raq_scsi_fixup(struct pci_dev *dev) in qube_raq_scsi_fixup() argument
176 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_SCSI_IRQ); in qube_raq_scsi_fixup()
177 dev->irq = COBALT_SCSI_IRQ; in qube_raq_scsi_fixup()
182 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); in qube_raq_scsi_fixup()
186 pci_write_config_word(dev, PCI_COMMAND, pci_cmd); in qube_raq_scsi_fixup()
189 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, COBALT_RAQ_SCSI_IRQ); in qube_raq_scsi_fixup()
190 dev->irq = COBALT_RAQ_SCSI_IRQ; in qube_raq_scsi_fixup()
195 dev->resource[0].start = 0x102000; in qube_raq_scsi_fixup()
196 dev->resource[0].end = dev->resource[0].start + 0xff; in qube_raq_scsi_fixup()
197 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x10102000); in qube_raq_scsi_fixup()
199 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0x00002000); in qube_raq_scsi_fixup()
200 pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0x00100000); in qube_raq_scsi_fixup()
204 static void qube_raq_galileo_fixup(struct pci_dev *dev) in qube_raq_galileo_fixup() argument
211 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); in qube_raq_galileo_fixup()
212 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7); in qube_raq_galileo_fixup()
221 pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id); in qube_raq_galileo_fixup()
236 qube_pcibios_fixup(struct pci_dev *dev) in qube_pcibios_fixup() argument
238 if (PCI_SLOT(dev->devfn) == COBALT_PCICONF_PCISLOT) { in qube_pcibios_fixup()
244 pci_read_config_dword(dev, PCI_VENDOR_ID, &tmp); in qube_pcibios_fixup()
246 qube_expansion_slot_fixup(dev); in qube_pcibios_fixup()
259 static __inline__ int pci_range_ck(struct pci_dev *dev) in pci_range_ck() argument
261 if ((dev->bus->number == 0) in pci_range_ck()
262 && ((PCI_SLOT (dev->devfn) == 0) in pci_range_ck()
263 || ((PCI_SLOT (dev->devfn) > 6) in pci_range_ck()
264 && (PCI_SLOT (dev->devfn) <= 12)))) in pci_range_ck()
270 #define PCI_CFG_SET(dev,where) \ argument
271 GALILEO_OUTL((0x80000000 | (((dev)->devfn) << 8) | \
274 static int qube_pci_read_config_dword (struct pci_dev *dev, in qube_pci_read_config_dword() argument
280 if (pci_range_ck (dev)) { in qube_pci_read_config_dword()
284 PCI_CFG_SET(dev, where); in qube_pci_read_config_dword()
289 static int qube_pci_read_config_word (struct pci_dev *dev, in qube_pci_read_config_word() argument
295 if (pci_range_ck (dev)) { in qube_pci_read_config_word()
299 PCI_CFG_SET(dev, (where & ~0x3)); in qube_pci_read_config_word()
304 static int qube_pci_read_config_byte (struct pci_dev *dev, in qube_pci_read_config_byte() argument
308 if (pci_range_ck (dev)) { in qube_pci_read_config_byte()
312 PCI_CFG_SET(dev, (where & ~0x3)); in qube_pci_read_config_byte()
317 static int qube_pci_write_config_dword (struct pci_dev *dev, in qube_pci_write_config_dword() argument
323 if (pci_range_ck (dev)) in qube_pci_write_config_dword()
325 PCI_CFG_SET(dev, where); in qube_pci_write_config_dword()
331 qube_pci_write_config_word (struct pci_dev *dev, in qube_pci_write_config_word() argument
339 if (pci_range_ck (dev)) in qube_pci_write_config_word()
341 PCI_CFG_SET(dev, (where & ~0x3)); in qube_pci_write_config_word()
350 qube_pci_write_config_byte (struct pci_dev *dev, in qube_pci_write_config_byte() argument
356 if (pci_range_ck (dev)) in qube_pci_write_config_byte()
358 PCI_CFG_SET(dev, (where & ~0x3)); in qube_pci_write_config_byte()
378 struct pci_dev dev; in pcibios_init() local
383 dev.devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0); in pcibios_init()
384 PCI_CFG_SET(&dev, (VIA_COBALT_BRD_ID_REG & ~0x3)); in pcibios_init()