Lines Matching refs:au_writel
115 au_writel(1<<(irq_nr-32), IC1_MASKSET); in local_enable_irq()
116 au_writel(1<<(irq_nr-32), IC1_WAKESET); in local_enable_irq()
119 au_writel(1<<irq_nr, IC0_MASKSET); in local_enable_irq()
120 au_writel(1<<irq_nr, IC0_WAKESET); in local_enable_irq()
129 au_writel(1<<(irq_nr-32), IC1_MASKCLR); in local_disable_irq()
130 au_writel(1<<(irq_nr-32), IC1_WAKECLR); in local_disable_irq()
133 au_writel(1<<irq_nr, IC0_MASKCLR); in local_disable_irq()
134 au_writel(1<<irq_nr, IC0_WAKECLR); in local_disable_irq()
143 au_writel(1<<(irq_nr-32), IC1_RISINGCLR); in mask_and_ack_rise_edge_irq()
144 au_writel(1<<(irq_nr-32), IC1_MASKCLR); in mask_and_ack_rise_edge_irq()
147 au_writel(1<<irq_nr, IC0_RISINGCLR); in mask_and_ack_rise_edge_irq()
148 au_writel(1<<irq_nr, IC0_MASKCLR); in mask_and_ack_rise_edge_irq()
157 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR); in mask_and_ack_fall_edge_irq()
158 au_writel(1<<(irq_nr-32), IC1_MASKCLR); in mask_and_ack_fall_edge_irq()
161 au_writel(1<<irq_nr, IC0_FALLINGCLR); in mask_and_ack_fall_edge_irq()
162 au_writel(1<<irq_nr, IC0_MASKCLR); in mask_and_ack_fall_edge_irq()
174 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR); in mask_and_ack_either_edge_irq()
175 au_writel(1<<(irq_nr-32), IC1_RISINGCLR); in mask_and_ack_either_edge_irq()
176 au_writel(1<<(irq_nr-32), IC1_MASKCLR); in mask_and_ack_either_edge_irq()
179 au_writel(1<<irq_nr, IC0_FALLINGCLR); in mask_and_ack_either_edge_irq()
180 au_writel(1<<irq_nr, IC0_RISINGCLR); in mask_and_ack_either_edge_irq()
181 au_writel(1<<irq_nr, IC0_MASKCLR); in mask_and_ack_either_edge_irq()
194 au_writel(0x8000, PB1000_MDR); /* ack int */ in mask_and_ack_level_irq()
209 au_writel(0x4000, PB1000_MDR); /* enable int */ in end_irq()
319 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); in setup_local_irq()
320 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); in setup_local_irq()
321 au_writel(1<<(irq_nr-32), IC1_CFG0SET); in setup_local_irq()
325 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); in setup_local_irq()
326 au_writel(1<<(irq_nr-32), IC1_CFG1SET); in setup_local_irq()
327 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); in setup_local_irq()
331 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); in setup_local_irq()
332 au_writel(1<<(irq_nr-32), IC1_CFG1SET); in setup_local_irq()
333 au_writel(1<<(irq_nr-32), IC1_CFG0SET); in setup_local_irq()
337 au_writel(1<<(irq_nr-32), IC1_CFG2SET); in setup_local_irq()
338 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); in setup_local_irq()
339 au_writel(1<<(irq_nr-32), IC1_CFG0SET); in setup_local_irq()
343 au_writel(1<<(irq_nr-32), IC1_CFG2SET); in setup_local_irq()
344 au_writel(1<<(irq_nr-32), IC1_CFG1SET); in setup_local_irq()
345 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); in setup_local_irq()
349 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); in setup_local_irq()
350 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); in setup_local_irq()
351 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); in setup_local_irq()
355 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); in setup_local_irq()
356 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); in setup_local_irq()
357 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); in setup_local_irq()
361 au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR); in setup_local_irq()
363 au_writel(1<<(irq_nr-32), IC1_ASSIGNSET); in setup_local_irq()
364 au_writel(1<<(irq_nr-32), IC1_SRCSET); in setup_local_irq()
365 au_writel(1<<(irq_nr-32), IC1_MASKCLR); in setup_local_irq()
366 au_writel(1<<(irq_nr-32), IC1_WAKECLR); in setup_local_irq()
371 au_writel(1<<irq_nr, IC0_CFG2CLR); in setup_local_irq()
372 au_writel(1<<irq_nr, IC0_CFG1CLR); in setup_local_irq()
373 au_writel(1<<irq_nr, IC0_CFG0SET); in setup_local_irq()
377 au_writel(1<<irq_nr, IC0_CFG2CLR); in setup_local_irq()
378 au_writel(1<<irq_nr, IC0_CFG1SET); in setup_local_irq()
379 au_writel(1<<irq_nr, IC0_CFG0CLR); in setup_local_irq()
383 au_writel(1<<irq_nr, IC0_CFG2CLR); in setup_local_irq()
384 au_writel(1<<irq_nr, IC0_CFG1SET); in setup_local_irq()
385 au_writel(1<<irq_nr, IC0_CFG0SET); in setup_local_irq()
389 au_writel(1<<irq_nr, IC0_CFG2SET); in setup_local_irq()
390 au_writel(1<<irq_nr, IC0_CFG1CLR); in setup_local_irq()
391 au_writel(1<<irq_nr, IC0_CFG0SET); in setup_local_irq()
395 au_writel(1<<irq_nr, IC0_CFG2SET); in setup_local_irq()
396 au_writel(1<<irq_nr, IC0_CFG1SET); in setup_local_irq()
397 au_writel(1<<irq_nr, IC0_CFG0CLR); in setup_local_irq()
401 au_writel(1<<irq_nr, IC0_CFG0CLR); in setup_local_irq()
402 au_writel(1<<irq_nr, IC0_CFG1CLR); in setup_local_irq()
403 au_writel(1<<irq_nr, IC0_CFG2CLR); in setup_local_irq()
407 au_writel(1<<irq_nr, IC0_CFG0CLR); in setup_local_irq()
408 au_writel(1<<irq_nr, IC0_CFG1CLR); in setup_local_irq()
409 au_writel(1<<irq_nr, IC0_CFG2CLR); in setup_local_irq()
413 au_writel(1<<irq_nr, IC0_ASSIGNCLR); in setup_local_irq()
415 au_writel(1<<irq_nr, IC0_ASSIGNSET); in setup_local_irq()
416 au_writel(1<<irq_nr, IC0_SRCSET); in setup_local_irq()
417 au_writel(1<<irq_nr, IC0_MASKCLR); in setup_local_irq()
418 au_writel(1<<irq_nr, IC0_WAKECLR); in setup_local_irq()
442 au_writel(0xffffffff, IC0_CFG0CLR); in init_IRQ()
443 au_writel(0xffffffff, IC0_CFG1CLR); in init_IRQ()
444 au_writel(0xffffffff, IC0_CFG2CLR); in init_IRQ()
445 au_writel(0xffffffff, IC0_MASKCLR); in init_IRQ()
446 au_writel(0xffffffff, IC0_ASSIGNSET); in init_IRQ()
447 au_writel(0xffffffff, IC0_WAKECLR); in init_IRQ()
448 au_writel(0xffffffff, IC0_SRCSET); in init_IRQ()
449 au_writel(0xffffffff, IC0_FALLINGCLR); in init_IRQ()
450 au_writel(0xffffffff, IC0_RISINGCLR); in init_IRQ()
451 au_writel(0x00000000, IC0_TESTBIT); in init_IRQ()
453 au_writel(0xffffffff, IC1_CFG0CLR); in init_IRQ()
454 au_writel(0xffffffff, IC1_CFG1CLR); in init_IRQ()
455 au_writel(0xffffffff, IC1_CFG2CLR); in init_IRQ()
456 au_writel(0xffffffff, IC1_MASKCLR); in init_IRQ()
457 au_writel(0xffffffff, IC1_ASSIGNSET); in init_IRQ()
458 au_writel(0xffffffff, IC1_WAKECLR); in init_IRQ()
459 au_writel(0xffffffff, IC1_SRCSET); in init_IRQ()
460 au_writel(0xffffffff, IC1_FALLINGCLR); in init_IRQ()
461 au_writel(0xffffffff, IC1_RISINGCLR); in init_IRQ()
462 au_writel(0x00000000, IC1_TESTBIT); in init_IRQ()
629 au_writel(0xffffffff, IC0_MASKCLR); au_sync(); in restore_au1xxx_intctl()
631 au_writel(0xffffffff, IC0_CFG0CLR); au_sync(); in restore_au1xxx_intctl()
632 au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync(); in restore_au1xxx_intctl()
633 au_writel(0xffffffff, IC0_CFG1CLR); au_sync(); in restore_au1xxx_intctl()
634 au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync(); in restore_au1xxx_intctl()
635 au_writel(0xffffffff, IC0_CFG2CLR); au_sync(); in restore_au1xxx_intctl()
636 au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync(); in restore_au1xxx_intctl()
637 au_writel(0xffffffff, IC0_SRCCLR); au_sync(); in restore_au1xxx_intctl()
638 au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync(); in restore_au1xxx_intctl()
639 au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync(); in restore_au1xxx_intctl()
640 au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync(); in restore_au1xxx_intctl()
641 au_writel(0xffffffff, IC0_WAKECLR); au_sync(); in restore_au1xxx_intctl()
642 au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync(); in restore_au1xxx_intctl()
643 au_writel(0xffffffff, IC0_RISINGCLR); au_sync(); in restore_au1xxx_intctl()
644 au_writel(0xffffffff, IC0_FALLINGCLR); au_sync(); in restore_au1xxx_intctl()
645 au_writel(0x00000000, IC0_TESTBIT); au_sync(); in restore_au1xxx_intctl()
647 au_writel(0xffffffff, IC1_MASKCLR); au_sync(); in restore_au1xxx_intctl()
649 au_writel(0xffffffff, IC1_CFG0CLR); au_sync(); in restore_au1xxx_intctl()
650 au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync(); in restore_au1xxx_intctl()
651 au_writel(0xffffffff, IC1_CFG1CLR); au_sync(); in restore_au1xxx_intctl()
652 au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync(); in restore_au1xxx_intctl()
653 au_writel(0xffffffff, IC1_CFG2CLR); au_sync(); in restore_au1xxx_intctl()
654 au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync(); in restore_au1xxx_intctl()
655 au_writel(0xffffffff, IC1_SRCCLR); au_sync(); in restore_au1xxx_intctl()
656 au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync(); in restore_au1xxx_intctl()
657 au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync(); in restore_au1xxx_intctl()
658 au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync(); in restore_au1xxx_intctl()
659 au_writel(0xffffffff, IC1_WAKECLR); au_sync(); in restore_au1xxx_intctl()
660 au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync(); in restore_au1xxx_intctl()
661 au_writel(0xffffffff, IC1_RISINGCLR); au_sync(); in restore_au1xxx_intctl()
662 au_writel(0xffffffff, IC1_FALLINGCLR); au_sync(); in restore_au1xxx_intctl()
663 au_writel(0x00000000, IC1_TESTBIT); au_sync(); in restore_au1xxx_intctl()
665 au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync(); in restore_au1xxx_intctl()
667 au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync(); in restore_au1xxx_intctl()