Lines Matching refs:slot
41 int pcibr_slot_info_init(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
42 int pcibr_slot_info_free(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
43 int pcibr_slot_addr_space_init(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
44 int pcibr_slot_pcix_rbar_init(pcibr_soft_t pcibr_soft, pciio_slot_t slot);
45 int pcibr_slot_device_init(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
46 int pcibr_slot_guest_info_init(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot);
48 pciio_slot_t slot, int drv_flags);
50 pciio_slot_t slot, int drv_flags);
51 int pcibr_slot_detach(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot,
62 int pcibr_slot_attach(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot,
65 int pcibr_slot_info_return(pcibr_soft_t pcibr_soft, pciio_slot_t slot,
109 pciio_slot_t slot; in pcibr_slot_startup() local
120 slot = PCIBR_SLOT_TO_DEVICE(pcibr_soft, reqp->req_slot); in pcibr_slot_startup()
123 if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) in pcibr_slot_startup()
131 if (pcibr_soft->bs_slot[slot].slot_status & SLOT_STARTUP_CMPLT) { in pcibr_slot_startup()
136 error = pcibr_slot_attach(pcibr_vhdl, slot, D_PCI_HOT_PLUG_ATTACH, in pcibr_slot_startup()
164 pciio_slot_t slot; in pcibr_slot_shutdown() local
176 slot = PCIBR_SLOT_TO_DEVICE(pcibr_soft, reqp->req_slot); in pcibr_slot_shutdown()
181 if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) in pcibr_slot_shutdown()
189 if ((pcibr_soft->bs_slot[slot].slot_status & SLOT_SHUTDOWN_CMPLT) || in pcibr_slot_shutdown()
190 ((pcibr_soft->bs_slot[slot].slot_status & SLOT_STATUS_MASK) == 0)) { in pcibr_slot_shutdown()
200 if (pcibr_soft->bs_slot[slot].bss_ninfo > 1) { in pcibr_slot_shutdown()
211 if (tmp_slot != slot) in pcibr_slot_shutdown()
222 error = pcibr_slot_detach(pcibr_vhdl, slot, D_PCI_HOT_PLUG_DETACH, in pcibr_slot_shutdown()
317 pciio_slot_t slot, in pcibr_slot_info_return() argument
332 pss = &pcibr_soft->bs_slot[slot]; in pcibr_slot_info_return()
373 slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot][VCHAN0]; in pcibr_slot_info_return()
374 slotp->resp_bs_rrb_valid_v1 = pcibr_soft->bs_rrb_valid[slot][VCHAN1]; in pcibr_slot_info_return()
375 slotp->resp_bs_rrb_valid_v2 = pcibr_soft->bs_rrb_valid[slot][VCHAN2]; in pcibr_slot_info_return()
376 slotp->resp_bs_rrb_valid_v3 = pcibr_soft->bs_rrb_valid[slot][VCHAN3]; in pcibr_slot_info_return()
377 slotp->resp_bs_rrb_res = pcibr_soft->bs_rrb_res[slot]; in pcibr_slot_info_return()
379 if (slot & 1) { in pcibr_slot_info_return()
391 slotp->resp_p_int_host = bridge->p_int_addr_64[slot]; in pcibr_slot_info_return()
394 slotp->resp_b_int_host = bridge->b_int_addr[slot].addr; in pcibr_slot_info_return()
432 pciio_slot_t slot; in pcibr_slot_query() local
444 slot = PCIBR_SLOT_TO_DEVICE(pcibr_soft, reqp->req_slot); in pcibr_slot_query()
448 pcibr_soft, slot, reqp)); in pcibr_slot_query()
451 if ((!PCIBR_VALID_SLOT(pcibr_soft, slot)) && (slot != PCIIO_SLOT_NONE)) { in pcibr_slot_query()
456 if (slot != PCIIO_SLOT_NONE) { in pcibr_slot_query()
465 error = pcibr_slot_info_return(pcibr_soft, slot, respp); in pcibr_slot_query()
515 pciio_slot_t slot) in pcibr_slot_info_init() argument
546 if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) in pcibr_slot_info_init()
552 if (pcibr_soft->bs_slot[slot].has_host) { in pcibr_slot_info_init()
557 cfgw = pcibr_slot_config_addr(bridge, slot, 0); in pcibr_slot_info_init()
568 slotp = &pcibr_soft->bs_slot[slot]; in pcibr_slot_info_init()
576 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), vendor, device)); in pcibr_slot_info_init()
596 cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0); in pcibr_slot_info_init()
615 cfgw = pcibr_slot_config_addr(bridge, slot, 0); in pcibr_slot_info_init()
619 pcibr_soft->bs_slot[slot].bss_ninfo = nfunc; in pcibr_slot_info_init()
620 pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh; in pcibr_slot_info_init()
630 cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0); in pcibr_slot_info_init()
640 pcibr_soft->bs_name, slot, func, htype); in pcibr_slot_info_init()
648 PCIBR_DEVICE_TO_SLOT(pcibr_soft,slot), func, cfgw)); in pcibr_slot_info_init()
695 if ((lt_time == 0) && !(bridge->b_device[slot].reg & BRIDGE_DEV_RT) && in pcibr_slot_info_init()
725 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func, lt_time)); in pcibr_slot_info_init()
741 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func)); in pcibr_slot_info_init()
753 "func %d not PCI-X capable\n", pcibr_vhdl, slot, func); in pcibr_slot_info_init()
756 "func %d not PCI-X capable\n", (unsigned long)pcibr_vhdl, slot, func); in pcibr_slot_info_init()
758 pcibr_device_info_new(pcibr_soft, slot, PCIIO_FUNC_NONE, in pcibr_slot_info_init()
765 pcix_cap, PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func)); in pcibr_slot_info_init()
771 (pcibr_soft, slot, rfunc, vendor, device); in pcibr_slot_info_init()
944 pciio_slot_t slot) in pcibr_slot_info_free() argument
955 if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) in pcibr_slot_info_free()
958 nfunc = pcibr_soft->bs_slot[slot].bss_ninfo; in pcibr_slot_info_free()
960 pcibr_device_info_free(pcibr_vhdl, slot); in pcibr_slot_info_free()
962 pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos; in pcibr_slot_info_free()
964 pcibr_soft->bs_slot[slot].bss_ninfo = 0; in pcibr_slot_info_free()
975 pciio_slot_t slot) in pcibr_slot_pcix_rbar_init() argument
983 if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) in pcibr_slot_pcix_rbar_init()
986 if ((nfunc = pcibr_soft->bs_slot[slot].bss_ninfo) < 1) in pcibr_slot_pcix_rbar_init()
989 if (!(pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos)) in pcibr_slot_pcix_rbar_init()
994 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot))); in pcibr_slot_pcix_rbar_init()
1060 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), func, in pcibr_slot_pcix_rbar_init()
1080 pciio_slot_t slot) in pcibr_slot_addr_space_init() argument
1100 if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) in pcibr_slot_addr_space_init()
1109 if (pcibr_soft->bs_slot[slot].has_host) { in pcibr_slot_addr_space_init()
1113 nfunc = pcibr_soft->bs_slot[slot].bss_ninfo; in pcibr_slot_addr_space_init()
1117 pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos; in pcibr_slot_addr_space_init()
1155 cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0); in pcibr_slot_addr_space_init()
1182 "prom\n", PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), in pcibr_slot_addr_space_init()
1233 PCIBR_DEVICE_TO_SLOT(pcibr_soft,slot), win, space)); in pcibr_slot_addr_space_init()
1244 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), in pcibr_slot_addr_space_init()
1253 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), in pcibr_slot_addr_space_init()
1283 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), in pcibr_slot_addr_space_init()
1339 pciio_slot_t slot) in pcibr_slot_device_init() argument
1350 if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) in pcibr_slot_device_init()
1359 devreg = bridge->b_device[slot].reg; in pcibr_slot_device_init()
1373 pcibr_soft->bs_slot[slot].bss_device = devreg; in pcibr_slot_device_init()
1374 bridge->b_device[slot].reg = devreg; in pcibr_slot_device_init()
1379 slot, devreg, device_bits)); in pcibr_slot_device_init()
1390 pciio_slot_t slot) in pcibr_slot_guest_info_init() argument
1402 if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) in pcibr_slot_guest_info_init()
1405 slotp = &pcibr_soft->bs_slot[slot]; in pcibr_slot_guest_info_init()
1412 if (pcibr_soft->bs_slot[slot].bss_ninfo < 1) { in pcibr_slot_guest_info_init()
1414 pcibr_soft->bs_slot[slot].bss_ninfo = 1; in pcibr_slot_guest_info_init()
1415 pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh; in pcibr_slot_guest_info_init()
1418 (pcibr_soft, slot, PCIIO_FUNC_NONE, in pcibr_slot_guest_info_init()
1421 if (pcibr_soft->bs_slot[slot].has_host) { in pcibr_slot_guest_info_init()
1429 if (pcibr_soft->bs_slot[slot].has_host) { in pcibr_slot_guest_info_init()
1430 int host = pcibr_soft->bs_slot[slot].host_slot; in pcibr_slot_guest_info_init()
1459 pciio_slot_t slot, in pcibr_slot_call_device_attach() argument
1483 if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) in pcibr_slot_call_device_attach()
1486 if (pcibr_soft->bs_slot[slot].has_host) { in pcibr_slot_call_device_attach()
1492 nfunc = pcibr_soft->bs_slot[slot].bss_ninfo; in pcibr_slot_call_device_attach()
1493 pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos; in pcibr_slot_call_device_attach()
1555 pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK; in pcibr_slot_call_device_attach()
1556 pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT; in pcibr_slot_call_device_attach()
1559 pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK; in pcibr_slot_call_device_attach()
1560 pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT; in pcibr_slot_call_device_attach()
1573 pciio_slot_t slot, in pcibr_slot_call_device_detach() argument
1591 if (!PCIBR_VALID_SLOT(pcibr_soft, slot)) in pcibr_slot_call_device_detach()
1594 if (pcibr_soft->bs_slot[slot].has_host) in pcibr_slot_call_device_detach()
1597 nfunc = pcibr_soft->bs_slot[slot].bss_ninfo; in pcibr_slot_call_device_detach()
1598 pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos; in pcibr_slot_call_device_detach()
1634 pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK; in pcibr_slot_call_device_detach()
1635 pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT; in pcibr_slot_call_device_detach()
1640 pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK; in pcibr_slot_call_device_detach()
1641 pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT; in pcibr_slot_call_device_detach()
1656 pciio_slot_t slot, in pcibr_slot_attach() argument
1668 if (pcibr_soft->bs_slot[slot].bss_ninfo > 1) { in pcibr_slot_attach()
1675 error = pcibr_slot_call_device_attach(pcibr_vhdl, slot, drv_flags); in pcibr_slot_attach()
1695 pciio_slot_t slot, in pcibr_slot_detach() argument
1704 error = (pcibr_slot_call_device_detach(pcibr_vhdl, slot, drv_flags)); in pcibr_slot_detach()
1784 pcibr_device_info_free(vertex_hdl_t pcibr_vhdl, pciio_slot_t slot) in pcibr_device_info_free() argument
1789 pcibr_soft_slot_t slotp = &pcibr_soft->bs_slot[slot]; in pcibr_device_info_free()
1808 cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0); in pcibr_device_info_free()