163     bridge_t                      *bridge;  in pcibr_slot_shutdown()  local
178     bridge = pcibr_soft->bs_base;  in pcibr_slot_shutdown()
207     if ((bridge->b_wid_control & BRIDGE_CTRL_BUS_SPEED_MASK) ==  in pcibr_slot_shutdown()
322     bridge_t                    *bridge = pcibr_soft->bs_base;  in pcibr_slot_info_return()  local
380         b_respp = &bridge->b_odd_resp;  in pcibr_slot_info_return()
382         b_respp = &bridge->b_even_resp;  in pcibr_slot_info_return()
387     slotp->resp_b_int_device = bridge->b_int_device;  in pcibr_slot_info_return()
390 	slotp->resp_p_int_enable = bridge->p_int_enable_64;  in pcibr_slot_info_return()
391 	slotp->resp_p_int_host = bridge->p_int_addr_64[slot];  in pcibr_slot_info_return()
393 	slotp->resp_b_int_enable = bridge->b_int_enable;  in pcibr_slot_info_return()
394 	slotp->resp_b_int_host = bridge->b_int_addr[slot].addr;  in pcibr_slot_info_return()
520     bridge_t		   *bridge;  in pcibr_slot_info_init()  local
545     bridge = pcibr_soft->bs_base;  in pcibr_slot_info_init()
557     cfgw = pcibr_slot_config_addr(bridge, slot, 0);  in pcibr_slot_info_init()
562     if (pcibr_probe_slot(bridge, cfgw, &idword))   in pcibr_slot_info_init()
596 	    cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0);  in pcibr_slot_info_init()
600 	    if (pcibr_probe_slot(bridge, cfgw, &idwords[func])) {  in pcibr_slot_info_init()
615         cfgw = pcibr_slot_config_addr(bridge, slot, 0);  in pcibr_slot_info_init()
630 	    cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0);  in pcibr_slot_info_init()
695 	if ((lt_time == 0) && !(bridge->b_device[slot].reg & BRIDGE_DEV_RT) &&  in pcibr_slot_info_init()
1085     bridge_t		*bridge;  in pcibr_slot_addr_space_init()  local
1103     bridge = pcibr_soft->bs_base;  in pcibr_slot_addr_space_init()
1155         cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0);  in pcibr_slot_addr_space_init()
1342     bridge_t		*bridge;  in pcibr_slot_device_init()  local
1353     bridge = pcibr_soft->bs_base;  in pcibr_slot_device_init()
1359     devreg = bridge->b_device[slot].reg;  in pcibr_slot_device_init()
1374     bridge->b_device[slot].reg = devreg;  in pcibr_slot_device_init()
1739 pcibr_probe_slot_pic(bridge_t *bridge,  in pcibr_probe_slot_pic()  argument
1746 	p_old_enable = bridge->p_int_enable_64;  in pcibr_probe_slot_pic()
1748 	bridge->p_int_enable_64 = p_new_enable;  in pcibr_probe_slot_pic()
1750 	if (bridge->p_err_int_view_64 & (BRIDGE_ISR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT))  in pcibr_probe_slot_pic()
1751 		bridge->p_int_rst_stat_64 = BRIDGE_IRR_MULTI_CLR;  in pcibr_probe_slot_pic()
1753 	if (bridge->p_int_status_64 & (BRIDGE_IRR_PCI_GRP | PIC_PCIX_GRP_CLR)) {  in pcibr_probe_slot_pic()
1754 		bridge->p_int_rst_stat_64 = (BRIDGE_IRR_PCI_GRP_CLR | PIC_PCIX_GRP_CLR);  in pcibr_probe_slot_pic()
1755 		(void) bridge->b_wid_tflush;	/* flushbus */  in pcibr_probe_slot_pic()
1758 	if (bridge->p_err_int_view_64 & (BRIDGE_ISR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT)) {  in pcibr_probe_slot_pic()
1759 		bridge->p_int_rst_stat_64 = BRIDGE_IRR_MULTI_CLR;  in pcibr_probe_slot_pic()
1762 	bridge->p_int_enable_64 = p_old_enable;  in pcibr_probe_slot_pic()
1763 	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */  in pcibr_probe_slot_pic()
1775 pcibr_probe_slot(bridge_t *bridge,  in pcibr_probe_slot()  argument
1779     return(pcibr_probe_slot_pic(bridge, cfg, valp));  in pcibr_probe_slot()
1790     bridge_t           *bridge = pcibr_soft->bs_base;   in pcibr_device_info_free()  local
1808 	cfgw = pcibr_func_config_addr(bridge, 0, slot, func, 0);  in pcibr_device_info_free()