71 #define RRB_ENABLE_BIT(bridge)		(0x8)  /* [BRIDGE | PIC]_RRB_EN */  argument
72 #define NUM_PDEV_BITS(bridge)		(1)  argument
73 #define NUM_VDEV_BITS(bridge)		(2)  argument
74 #define NUMBER_VCHANNELS(bridge)	(4)  argument
75 #define SLOT_2_PDEV(bridge, slot)	((slot) >> 1)  argument
76 #define SLOT_2_RRB_REG(bridge, slot)	((slot) & 0x1)  argument
79 #define VALIDATE_SLOT_n_VCHAN(bridge, s, v) \  argument
87 do_pcibr_rrb_count_valid(bridge_t *bridge,  in do_pcibr_rrb_count_valid()  argument
95     if (!VALIDATE_SLOT_n_VCHAN(bridge, slot, vchan)) {  in do_pcibr_rrb_count_valid()
100     enable_bit = RRB_ENABLE_BIT(bridge);  in do_pcibr_rrb_count_valid()
101     vchan_bits = vchan << NUM_PDEV_BITS(bridge);  in do_pcibr_rrb_count_valid()
102     pdev_bits = SLOT_2_PDEV(bridge, slot);  in do_pcibr_rrb_count_valid()
105     tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg;  in do_pcibr_rrb_count_valid()
121 do_pcibr_rrb_count_avail(bridge_t *bridge,  in do_pcibr_rrb_count_avail()  argument
128     if (!VALIDATE_SLOT_n_VCHAN(bridge, slot, 0)) {  in do_pcibr_rrb_count_avail()
133     enable_bit = RRB_ENABLE_BIT(bridge);  in do_pcibr_rrb_count_avail()
135     tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg;  in do_pcibr_rrb_count_avail()
155 do_pcibr_rrb_alloc(bridge_t *bridge,  in do_pcibr_rrb_alloc()  argument
164     if (!VALIDATE_SLOT_n_VCHAN(bridge, slot, vchan)) {  in do_pcibr_rrb_alloc()
169     enable_bit = RRB_ENABLE_BIT(bridge);  in do_pcibr_rrb_alloc()
170     vchan_bits = vchan << NUM_PDEV_BITS(bridge);  in do_pcibr_rrb_alloc()
171     pdev_bits = SLOT_2_PDEV(bridge, slot);  in do_pcibr_rrb_alloc()
174     reg = tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg;  in do_pcibr_rrb_alloc()
186     bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg = reg;  in do_pcibr_rrb_alloc()
200 do_pcibr_rrb_free(bridge_t *bridge,  in do_pcibr_rrb_free()  argument
209     if (!VALIDATE_SLOT_n_VCHAN(bridge, slot, vchan)) {  in do_pcibr_rrb_free()
214     enable_bit = RRB_ENABLE_BIT(bridge);  in do_pcibr_rrb_free()
215     vchan_bits = vchan << NUM_PDEV_BITS(bridge);  in do_pcibr_rrb_free()
216     pdev_bits = SLOT_2_PDEV(bridge, slot);  in do_pcibr_rrb_free()
219     reg = tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg;  in do_pcibr_rrb_free()
229 	    reg = reg & ~(RRB_ENABLE_BIT(bridge) << (RRB_SIZE * rrb_index));  in do_pcibr_rrb_free()
236     bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg = reg;  in do_pcibr_rrb_free()
240 	int evn_odd = SLOT_2_RRB_REG(bridge, slot);  in do_pcibr_rrb_free()
242 	    do_pcibr_rrb_clear(bridge, (2 * rrb_index) + evn_odd);  in do_pcibr_rrb_free()
255 		      bridge_t *bridge,  in do_pcibr_rrb_free_all()  argument
259     int vchan_total = NUMBER_VCHANNELS(bridge);  in do_pcibr_rrb_free_all()
263 	    (void)do_pcibr_rrb_free(bridge, slot, vchan, 8);  in do_pcibr_rrb_free_all()
275 do_pcibr_rrb_clear(bridge_t *bridge, int rrb)  in do_pcibr_rrb_clear()  argument
284     while ((status = bridge->b_resp_status) & BRIDGE_RRB_INUSE(rrb)) {  in do_pcibr_rrb_clear()
290 	bridge->b_resp_clear = BRIDGE_RRB_CLEAR(rrb);  in do_pcibr_rrb_clear()
293 	while ((status = bridge->b_resp_status) & BRIDGE_RRB_VALID(rrb)) {  in do_pcibr_rrb_clear()
306 do_pcibr_rrb_flush(bridge_t *bridge, int rrbn)  in do_pcibr_rrb_flush()  argument
308     reg_p	 rrbp = &bridge->b_rrb_map[rrbn & 1].reg;  in do_pcibr_rrb_flush()
311     unsigned long	 ebit = RRB_ENABLE_BIT(bridge) << shft;  in do_pcibr_rrb_flush()
319     do_pcibr_rrb_clear(bridge, rrbn);  in do_pcibr_rrb_flush()
333     bridge_t               *bridge = pcibr_soft->bs_base;  in do_pcibr_rrb_autoalloc()  local
343 	if (do_pcibr_rrb_alloc(bridge, slot, vchan, 1) < 0)  in do_pcibr_rrb_autoalloc()
367     bridge_t	 *bridge = pcibr_soft->bs_base;  in pcibr_rrb_flush()  local
374     enable_bit = RRB_ENABLE_BIT(bridge);  in pcibr_rrb_flush()
375     pdev_bits = SLOT_2_PDEV(bridge, slot);  in pcibr_rrb_flush()
377     rrb_mask = enable_bit | ((NUM_PDEV_BITS(bridge) << 1) - 1);  in pcibr_rrb_flush()
379     tmp = bridge->b_rrb_map[SLOT_2_RRB_REG(bridge, slot)].reg;  in pcibr_rrb_flush()
383 	int evn_odd = SLOT_2_RRB_REG(bridge, slot);  in pcibr_rrb_flush()
385 	    do_pcibr_rrb_flush(bridge, (2 * rrb_index) + evn_odd);  in pcibr_rrb_flush()
402     bridge_t               *bridge = pcibr_soft->bs_base;  in pcibr_wrb_flush()  local
405     wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg);  in pcibr_wrb_flush()
432     bridge_t               *bridge = pcibr_soft->bs_base;  in pcibr_rrb_alloc()  local
462     vchan_total = NUMBER_VCHANNELS(bridge);  in pcibr_rrb_alloc()
528 	    (void) do_pcibr_rrb_free(bridge, pciio_slot, VCHAN0, -delta_vchan0);  in pcibr_rrb_alloc()
530 	    (void) do_pcibr_rrb_free(bridge, pciio_slot, VCHAN1, -delta_vchan1);  in pcibr_rrb_alloc()
533 	    (void) do_pcibr_rrb_alloc(bridge, pciio_slot, VCHAN0, delta_vchan0);  in pcibr_rrb_alloc()
535 	    (void) do_pcibr_rrb_alloc(bridge, pciio_slot, VCHAN1, delta_vchan1);  in pcibr_rrb_alloc()
687     bridge_t		*bridge;  in pcibr_slot_initial_rrb_alloc()  local
700     bridge = pcibr_soft->bs_base;  in pcibr_slot_initial_rrb_alloc()
703     vchan_total = NUMBER_VCHANNELS(bridge);  in pcibr_slot_initial_rrb_alloc()
705         chan[vchan] = do_pcibr_rrb_count_valid(bridge, slot, vchan);  in pcibr_slot_initial_rrb_alloc()
730             do_pcibr_rrb_free(bridge, slot, vchan, 8);  in pcibr_slot_initial_rrb_alloc()
741 	do_pcibr_rrb_free_all(pcibr_soft, bridge, slot);  in pcibr_slot_initial_rrb_alloc()
778     bridge_t               *bridge = pcibr_soft->bs_base;  in pcibr_initial_rrb()  local
791     vchan_total = NUMBER_VCHANNELS(bridge);  in pcibr_initial_rrb()
810     pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0);  in pcibr_initial_rrb()
811     pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1);  in pcibr_initial_rrb()