Lines Matching refs:bridge
83 pcibr_init_ext_ate_ram(bridge_t *bridge) in pcibr_init_ext_ate_ram() argument
91 old_enable = bridge->b_int_enable; in pcibr_init_ext_ate_ram()
93 bridge->b_int_enable = new_enable; in pcibr_init_ext_ate_ram()
97 bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE; in pcibr_init_ext_ate_ram()
101 bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(j) - 1] = 0; in pcibr_init_ext_ate_ram()
104 if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE) in pcibr_init_ext_ate_ram()
107 bridge->b_int_enable = old_enable; in pcibr_init_ext_ate_ram()
108 bridge->b_wid_tflush; /* wait until Bridge PIO complete */ in pcibr_init_ext_ate_ram()
115 bridge->b_wid_control = (bridge->b_wid_control in pcibr_init_ext_ate_ram()
118 bridge->b_wid_control; /* inval addr bug war */ in pcibr_init_ext_ate_ram()
126 bridge, num_entries)); in pcibr_init_ext_ate_ram()
130 bridge)); in pcibr_init_ext_ate_ram()
136 bridge->b_ext_ate_ram[entry] = 0; in pcibr_init_ext_ate_ram()
266 bridge_t *bridge = pcibr_soft->bs_base; in pcibr_ate_addr() local
269 ? &(bridge->b_int_ate_ram[ate_index].wr) in pcibr_ate_addr()
270 : &(bridge->b_ext_ate_ram[ate_index]); in pcibr_ate_addr()
353 bridge_t *bridge = pcibr_soft->bs_base; in ate_freeze() local
369 bridge->b_wr_req_buf[slot].reg; in ate_freeze()
408 bridge_t *bridge = pcibr_soft->bs_base; in ate_thaw() local
426 pcibr_slot_config_set(bridge, slot, PCI_CFG_COMMAND/4, cmd_reg); in ate_thaw()