40 #define PENDING(port) (PCI_INW(&(port)->ip_ioc4->sio_ir) & port->ip_ienb)
567 	    shadow = PCI_INW(&port->ip_serial->shadow);  in ioc4_serial_intr()
586 	    shadow = PCI_INW(&port->ip_serial->shadow);  in ioc4_serial_intr()
824     do sio_cr = PCI_INW(&port->ip_ioc4->sio_cr);  in hardware_init()
833     port->ip_tx_prod = PCI_INW(&port->ip_serial->stcir) & PROD_CONS_MASK;  in hardware_init()
836     port->ip_rx_cons = PCI_INW(&port->ip_serial->srpir) & PROD_CONS_MASK;  in hardware_init()
890 		tmp1 = PCI_INW(sbbr_l);  in hardware_init()
891 		tmp2 = PCI_INW(sbbr_h);  in hardware_init()
1311 	SPIN((PCI_INW(&p->ip_serial->sscr) & IOC4_SSCR_PAUSE_STATE) == 0,  in ioc4_open()
1395 	SPIN((PCI_INW(&p->ip_serial->sscr) & IOC4_SSCR_PAUSE_STATE) == 0,  in ioc4_config()
1508     cons_ptr = PCI_INW(&p->ip_serial->stcir) & PROD_CONS_MASK;  in do_ioc4_write()
1620     if (!(PCI_INW(&p->ip_ioc4->sio_ir) & IOC4_SIO_IR_S0_TX_MT) &&  in ioc4_wrflush()
1631     while ((PCI_INW(&p->ip_serial->sscr) & (IOC4_SSCR_DMA_EN |  in ioc4_wrflush()
1633 	   !(PCI_INW(&p->ip_ioc4->sio_ir) & IOC4_SIO_IR_S0_TX_MT)) {  in ioc4_wrflush()
1656 	SPIN((PCI_INW(&p->ip_serial->sscr) & IOC4_SSCR_PAUSE_STATE) == 0,  in ioc4_break()
1702 	SPIN((PCI_INW(&p->ip_serial->sscr) & IOC4_SSCR_PAUSE_STATE) == 0,  in ioc4_enable_tx()
1714 	ioc4reg_t txcons = PCI_INW(&p->ip_serial->stcir) & PROD_CONS_MASK;  in ioc4_enable_tx()
1781     prod_ptr = PCI_INW(&p->ip_serial->srpir) & PROD_CONS_MASK;  in ioc4_read()
1802 	prod_ptr = PCI_INW(&p->ip_serial->srpir) & PROD_CONS_MASK;  in ioc4_read()
1814 	    SPIN(PCI_INW(&p->ip_serial->sscr) & IOC4_SSCR_RX_DRAIN, spin_success);  in ioc4_read()
1821 	    prod_ptr = PCI_INW(&p->ip_serial->srpir) & PROD_CONS_MASK;  in ioc4_read()
2125 	SPIN((PCI_INW(&p->ip_serial->sscr) & IOC4_SSCR_PAUSE_STATE) == 0,  in set_DTRRTS()
2131     shadow = PCI_INW(&p->ip_serial->shadow);  in set_DTRRTS()
2192     shadow = PCI_INW(&p->ip_serial->shadow);  in ioc4_query_DCD()
2210     shadow = PCI_INW(&p->ip_serial->shadow);  in ioc4_query_CTS()