Lines Matching refs:d
77 move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
78 move.d $r0, [R_WAITSTATES]
80 move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
81 move.d $r0, [R_BUS_CONFIG]
84 move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
85 move.d $r0, [R_DRAM_CONFIG]
87 move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
88 move.d $r0, [R_DRAM_TIMING]
97 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
98 move.d $r0, [R_SDRAM_CONFIG]
107 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2
108 and.d 0x00ff0000, $r2
112 move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
113 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
114 move.d $r1, $r3
115 and.d 0x03, $r1 ; Get CAS latency
116 and.d 0x1000, $r3 ; 50 or 100 MHz?
120 cmp.d 0x00, $r1 ; CAS latency = 2?
123 or.d 0x20, $r2 ; CAS latency = 3
127 cmp.d 0x01, $r1 ; CAS latency = 2?
130 or.d 0x20, $r2 ; CAS latency = 3
132 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
133 and.d 0x800000, $r1 ; DRAM width is bit 23
140 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
141 and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
142 or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
143 move.d $r1, $r5
144 or.d 0x0000c000, $r1 ; ref = disable
146 or.d $r2, $r1
147 move.d $r1, [R_SDRAM_TIMING]
150 move.d 10000, $r2
155 move.d _sdram_commands_start, $r2
156 and.d 0x000fffff, $r2 ; Make sure commands are read from flash
157 move.d _sdram_commands_end, $r3
158 and.d 0x000fffff, $r3
159 1: clear.d $r4
162 or.d $r1, $r4
163 move.d $r4, [R_SDRAM_TIMING]
169 cmp.d $r2, $r3
172 move.d $r5, [R_SDRAM_TIMING]