668 #define SER_RXD_MASK         IO_MASK(R_SERIAL0_STATUS, rxd)
669 #define SER_DATA_AVAIL_MASK  IO_MASK(R_SERIAL0_STATUS, data_avail)
670 #define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
671 #define SER_PAR_ERR_MASK     IO_MASK(R_SERIAL0_STATUS, par_err)
672 #define SER_OVERRUN_MASK     IO_MASK(R_SERIAL0_STATUS, overrun)
698 | IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
701 | IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
704 | IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
707 | IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
1394 		 ~IO_MASK(R_TIMER_CTRL, timerdiv1) &  in start_flush_timer()
1395 		 ~IO_MASK(R_TIMER_CTRL, tm1) &  in start_flush_timer()
1396 		 ~IO_MASK(R_TIMER_CTRL, clksel1)) |   in start_flush_timer()
1402 		(r_timer_ctrl_shadow & ~IO_MASK(R_TIMER_CTRL, tm1)) |  in start_flush_timer()
1594 		(info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));  in e100_disable_rx()
1604 		(info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));  in e100_enable_rx()
1664 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==  in e100_disable_txdma_channel()
1666 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma6);  in e100_disable_txdma_channel()
1670 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==  in e100_disable_txdma_channel()
1672 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma8);  in e100_disable_txdma_channel()
1676 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==  in e100_disable_txdma_channel()
1678 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma2);  in e100_disable_txdma_channel()
1682 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==  in e100_disable_txdma_channel()
1684 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma4);  in e100_disable_txdma_channel()
1703 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma6);  in e100_enable_txdma_channel()
1706 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma8);  in e100_enable_txdma_channel()
1709 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma2);  in e100_enable_txdma_channel()
1712 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma4);  in e100_enable_txdma_channel()
1730 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==  in e100_disable_rxdma_channel()
1732 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma7);  in e100_disable_rxdma_channel()
1736 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==  in e100_disable_rxdma_channel()
1738 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma9);  in e100_disable_rxdma_channel()
1742 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==  in e100_disable_rxdma_channel()
1744 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma3);  in e100_disable_rxdma_channel()
1748 		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==  in e100_disable_rxdma_channel()
1750 			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma5);  in e100_disable_rxdma_channel()
1768 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma7);  in e100_enable_rxdma_channel()
1771 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma9);  in e100_enable_rxdma_channel()
1774 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma3);  in e100_enable_rxdma_channel()
1777 		genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma5);  in e100_enable_rxdma_channel()
2351 	if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {  in receive_chars_dma()
2890 	if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {  in handle_ser_rx_interrupt_no_dma()
2895 	if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |  in handle_ser_rx_interrupt_no_dma()
2896 			  IO_MASK(R_SERIAL0_READ, par_err) |  in handle_ser_rx_interrupt_no_dma()
2897 			  IO_MASK(R_SERIAL0_READ, overrun) )) {  in handle_ser_rx_interrupt_no_dma()
2910 		if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&  in handle_ser_rx_interrupt_no_dma()
2911 		     (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {  in handle_ser_rx_interrupt_no_dma()
2919 			if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {  in handle_ser_rx_interrupt_no_dma()
2950 				if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {  in handle_ser_rx_interrupt_no_dma()
2953 				} else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {  in handle_ser_rx_interrupt_no_dma()
2956 				} else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {  in handle_ser_rx_interrupt_no_dma()
2964 	} else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {  in handle_ser_rx_interrupt_no_dma()
2987 	if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {  in handle_ser_rx_interrupt_no_dma()
3010 	if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {  in handle_ser_rx_interrupt()
3249 		irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |  in ser_interrupt()
3250 				 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |  in ser_interrupt()
3251 				 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |  in ser_interrupt()
3252 				 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));  in ser_interrupt()
3279 		ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |  in ser_interrupt()
3280 					     IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |  in ser_interrupt()
3281 					     IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |  in ser_interrupt()
3282 					     IO_MASK(R_IRQ_MASK1_RD, ser3_ready));  in ser_interrupt()
3647 	info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
3648 			   IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
3649 			   IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
3652 	info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
3653 			   IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
3654 			   IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
3655 			   IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
3656 			   IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
4965 		if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) )