633 	*R_NETWORK_MGM_CTRL = IO_STATE(R_NETWORK_MGM_CTRL, mdoe, enable);  in e100_open()
636 		IO_STATE(R_IRQ_MASK0_CLR, overrun, clr) |  in e100_open()
637 		IO_STATE(R_IRQ_MASK0_CLR, underrun, clr) |  in e100_open()
638 		IO_STATE(R_IRQ_MASK0_CLR, excessive_col, clr);  in e100_open()
642 		IO_STATE(R_IRQ_MASK2_CLR, dma0_descr, clr) |  in e100_open()
643 		IO_STATE(R_IRQ_MASK2_CLR, dma0_eop, clr) |  in e100_open()
644 		IO_STATE(R_IRQ_MASK2_CLR, dma1_descr, clr) |  in e100_open()
645 		IO_STATE(R_IRQ_MASK2_CLR, dma1_eop, clr);  in e100_open()
711 		IO_STATE(R_NETWORK_GEN_CONFIG, phy,    mii_clk) |  in e100_open()
712 		IO_STATE(R_NETWORK_GEN_CONFIG, enable, on);  in e100_open()
715 		IO_STATE(R_NETWORK_TR_CTRL, clr_error, clr) |  in e100_open()
716 		IO_STATE(R_NETWORK_TR_CTRL, delay, none) |  in e100_open()
717 		IO_STATE(R_NETWORK_TR_CTRL, cancel, dont) |  in e100_open()
718 		IO_STATE(R_NETWORK_TR_CTRL, cd, enable) |  in e100_open()
719 		IO_STATE(R_NETWORK_TR_CTRL, retry, enable) |  in e100_open()
720 		IO_STATE(R_NETWORK_TR_CTRL, pad, enable) |  in e100_open()
721 		IO_STATE(R_NETWORK_TR_CTRL, crc, enable);  in e100_open()
729 		IO_STATE(R_IRQ_MASK2_SET, dma0_eop, set) |  in e100_open()
730 		IO_STATE(R_IRQ_MASK2_SET, dma1_eop, set);  in e100_open()
733 		IO_STATE(R_IRQ_MASK0_SET, overrun,       set) |  in e100_open()
734 		IO_STATE(R_IRQ_MASK0_SET, underrun,      set) |  in e100_open()
735 		IO_STATE(R_IRQ_MASK0_SET, excessive_col, set);  in e100_open()
739 	*R_DMA_CH0_CLR_INTR = IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do);  in e100_open()
740 	*R_DMA_CH1_CLR_INTR = IO_STATE(R_DMA_CH1_CLR_INTR, clr_eop, do);  in e100_open()
750 	*R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, start);  in e100_open()
1047 		IO_STATE(R_NETWORK_MGM_CTRL, mdoe, enable) |  in e100_send_mdio_bit()
1051 		IO_STATE(R_NETWORK_MGM_CTRL, mdoe, enable) |  in e100_send_mdio_bit()
1181 	  IO_STATE(R_IRQ_MASK2_CLR, dma0_eop, clr) |  in e100rxtx_interrupt()
1182 	  IO_STATE(R_IRQ_MASK2_CLR, dma1_eop, clr);  in e100rxtx_interrupt()
1185 	if (irqbits & IO_STATE(R_IRQ_MASK2_RD, dma1_eop, active)) {  in e100rxtx_interrupt()
1188 		*R_DMA_CH1_CLR_INTR = IO_STATE(R_DMA_CH1_CLR_INTR, clr_eop, do);  in e100rxtx_interrupt()
1199 			*R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, restart);  in e100rxtx_interrupt()
1202 				IO_STATE(R_DMA_CH1_CLR_INTR, clr_eop, do) |  in e100rxtx_interrupt()
1203 				IO_STATE(R_DMA_CH1_CLR_INTR, clr_descr, do);  in e100rxtx_interrupt()
1224 	if (irqbits & IO_STATE(R_IRQ_MASK2_RD, dma0_eop, active)) {  in e100rxtx_interrupt()
1226 		*R_DMA_CH0_CLR_INTR = IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do);  in e100rxtx_interrupt()
1232 	  IO_STATE(R_IRQ_MASK2_SET, dma0_eop, set) |  in e100rxtx_interrupt()
1233 	  IO_STATE(R_IRQ_MASK2_SET, dma1_eop, set);  in e100rxtx_interrupt()
1244 	if (irqbits & IO_STATE(R_IRQ_MASK0_RD, underrun, active)) {   in e100nw_interrupt()
1245 		*R_NETWORK_TR_CTRL = IO_STATE(R_NETWORK_TR_CTRL, clr_error, clr);  in e100nw_interrupt()
1251 	if (irqbits & IO_STATE(R_IRQ_MASK0_RD, overrun, active)) {   in e100nw_interrupt()
1256 	if (irqbits & IO_STATE(R_IRQ_MASK0_RD, excessive_col, active)) {   in e100nw_interrupt()
1257 		*R_NETWORK_TR_CTRL = IO_STATE(R_NETWORK_TR_CTRL, clr_error, clr);  in e100nw_interrupt()
1375 		IO_STATE(R_IRQ_MASK0_CLR, overrun, clr) |  in e100_close()
1376 		IO_STATE(R_IRQ_MASK0_CLR, underrun, clr) |  in e100_close()
1377 		IO_STATE(R_IRQ_MASK0_CLR, excessive_col, clr);  in e100_close()
1380 		IO_STATE(R_IRQ_MASK2_CLR, dma0_descr, clr) |  in e100_close()
1381 		IO_STATE(R_IRQ_MASK2_CLR, dma0_eop, clr) |  in e100_close()
1382 		IO_STATE(R_IRQ_MASK2_CLR, dma1_descr, clr) |  in e100_close()
1383 		IO_STATE(R_IRQ_MASK2_CLR, dma1_eop, clr);  in e100_close()
1684 	*R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, restart);  in e100_hardware_send_packet()