Lines Matching refs:ld

126 	ld	r9,0x08(r4)
148 	ld	r9, 0x08(r4)
150 	ld	r7, 0x10(r4)	/* 4 register stride copy is optimal  */
151 	ld	r8, 0x18(r4)	/* to hide 1st level cache latency.  */
152 	ld	r0, 0x20(r4)
157 	ld	r9, 0x28(r4)
158 	ld	r7, 0x30(r4)
159 	ld	r8, 0x38(r4)
160 	ld	r0, 0x40(r4)
165 	ld	r9, 0x48(r4)
166 	ld	r7, 0x50(r4)
167 	ld	r8, 0x58(r4)
168 	ld	r0, 0x60(r4)
173 	ld	r9, 0x68(r4)
174 	ld	r7, 0x70(r4)
175 	ld	r8, 0x78(r4)
191 	ld	r9, 0x08(r4)
192 	ld	r7, 0x10(r4)
193 	ld	r8, 0x18(r4)
210 	ld	r8,0x08(r4)