Lines Matching refs:r5
50 addis r5,r2,.LC__dl_hwcap@toc@ha
51 ld r5,.LC__dl_hwcap@toc@l(r5)
54 ld r5,RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(r5)
57 ld r5,0(r5)
59 andis. r5,r5,(PPC_FEATURE_HAS_ALTIVEC >> 16)
61 la r5,((JB_VRS)*8)(3)
62 andi. r6,r5,0xf
66 addi r6,r5,16
67 lvsl v0,0,r5
68 lvx v1,0,r5
69 addi r5,r5,32
76 load_misaligned_vmx_lo_loaded(v21,v22,v0,r5,r6)
77 load_misaligned_vmx_lo_loaded(v22,v23,v0,r6,r5)
78 load_misaligned_vmx_lo_loaded(v23,v24,v0,r5,r6)
79 load_misaligned_vmx_lo_loaded(v24,v25,v0,r6,r5)
80 load_misaligned_vmx_lo_loaded(v25,v26,v0,r5,r6)
81 load_misaligned_vmx_lo_loaded(v26,v27,v0,r6,r5)
82 load_misaligned_vmx_lo_loaded(v27,v28,v0,r5,r6)
83 load_misaligned_vmx_lo_loaded(v28,v29,v0,r6,r5)
84 load_misaligned_vmx_lo_loaded(v29,v30,v0,r5,r6)
85 load_misaligned_vmx_lo_loaded(v30,v31,v0,r6,r5)
86 lvx v1,0,r5
90 addi r6,r5,16
91 lvx v20,0,r5
92 addi r5,r5,32
95 lvx v22,0,r5
96 addi r5,r5,32
99 lvx v24,0,r5
100 addi r5,r5,32
103 lvx v26,0,r5
104 addi r5,r5,32
107 lvx v28,0,r5
108 addi r5,r5,32
111 lvx v30,0,r5
159 lwz r5,((JB_CR*8)+4)(r3) /* 32-bit CR. */
166 mtcrf 0xFF,r5