Lines Matching refs:a1
282 PTR_SUBU t0,a0,a1
313 xor t8,a1,a0
322 C_LDHI t8,0(a1)
323 PTR_ADDU a1,a1,a3
348 lb a3, 6(a1)
351 lb a3, 5(a1)
354 lb a3, 4(a1)
357 lb a3, 3(a1)
360 lb a3, 2(a1)
363 lb a3, 1(a1)
366 lb a3, 0(a1)
373 PTR_ADDU a1,a1,t8
376 andi t8,a1,(NSIZE-1)
418 PREFETCH_FOR_LOAD (0, a1)
419 PREFETCH_FOR_LOAD (1, a1)
420 PREFETCH_FOR_LOAD (2, a1)
421 PREFETCH_FOR_LOAD (3, a1)
446 C_LD t0,UNIT(0)(a1)
451 C_LD t1,UNIT(1)(a1)
465 C_LD REG2,UNIT(2)(a1)
466 C_LD REG3,UNIT(3)(a1)
467 C_LD REG4,UNIT(4)(a1)
468 C_LD REG5,UNIT(5)(a1)
469 C_LD REG6,UNIT(6)(a1)
470 C_LD REG7,UNIT(7)(a1)
472 PREFETCH_FOR_LOAD (3, a1)
474 PREFETCH_FOR_LOAD (4, a1)
485 C_LD t0,UNIT(8)(a1)
486 C_LD t1,UNIT(9)(a1)
487 C_LD REG2,UNIT(10)(a1)
488 C_LD REG3,UNIT(11)(a1)
489 C_LD REG4,UNIT(12)(a1)
490 C_LD REG5,UNIT(13)(a1)
491 C_LD REG6,UNIT(14)(a1)
492 C_LD REG7,UNIT(15)(a1)
494 PREFETCH_FOR_LOAD (5, a1)
506 PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */
516 PREFETCH_FOR_LOAD (0, a1)
521 C_LD t0,UNIT(0)(a1)
522 C_LD t1,UNIT(1)(a1)
523 C_LD REG2,UNIT(2)(a1)
524 C_LD REG3,UNIT(3)(a1)
525 C_LD REG4,UNIT(4)(a1)
526 C_LD REG5,UNIT(5)(a1)
527 C_LD REG6,UNIT(6)(a1)
528 C_LD REG7,UNIT(7)(a1)
529 PTR_ADDIU a1,a1,UNIT(8)
555 C_LD REG3,UNIT(0)(a1)
557 PTR_ADDIU a1,a1,UNIT(1)
569 lw REG3,0(a1)
572 PTR_ADDIU a1,a1,4
580 lb v1,0(a1)
582 PTR_ADDIU a1,a1,1
600 andi t9,a1,3
607 lw REG3,0(a1)
609 PTR_ADDIU a1,a1,4
631 C_LDHI v1,UNIT(0)(a1)
632 C_LDLO v1,UNITM1(1)(a1)
633 PTR_ADDU a1,a1,a3
655 PREFETCH_FOR_LOAD (0, a1)
656 PREFETCH_FOR_LOAD (1, a1)
657 PREFETCH_FOR_LOAD (2, a1)
675 PREFETCH_FOR_LOAD (3, a1)
676 C_LDHI t0,UNIT(0)(a1)
677 C_LDHI t1,UNIT(1)(a1)
678 C_LDHI REG2,UNIT(2)(a1)
683 C_LDHI REG3,UNIT(3)(a1)
687 C_LDHI REG4,UNIT(4)(a1)
688 C_LDHI REG5,UNIT(5)(a1)
689 C_LDHI REG6,UNIT(6)(a1)
690 C_LDHI REG7,UNIT(7)(a1)
691 C_LDLO t0,UNITM1(1)(a1)
692 C_LDLO t1,UNITM1(2)(a1)
693 C_LDLO REG2,UNITM1(3)(a1)
694 C_LDLO REG3,UNITM1(4)(a1)
695 C_LDLO REG4,UNITM1(5)(a1)
696 C_LDLO REG5,UNITM1(6)(a1)
697 C_LDLO REG6,UNITM1(7)(a1)
698 C_LDLO REG7,UNITM1(8)(a1)
699 PREFETCH_FOR_LOAD (4, a1)
708 C_LDHI t0,UNIT(8)(a1)
709 C_LDHI t1,UNIT(9)(a1)
710 C_LDHI REG2,UNIT(10)(a1)
711 C_LDHI REG3,UNIT(11)(a1)
712 C_LDHI REG4,UNIT(12)(a1)
713 C_LDHI REG5,UNIT(13)(a1)
714 C_LDHI REG6,UNIT(14)(a1)
715 C_LDHI REG7,UNIT(15)(a1)
716 C_LDLO t0,UNITM1(9)(a1)
717 C_LDLO t1,UNITM1(10)(a1)
718 C_LDLO REG2,UNITM1(11)(a1)
719 C_LDLO REG3,UNITM1(12)(a1)
720 C_LDLO REG4,UNITM1(13)(a1)
721 C_LDLO REG5,UNITM1(14)(a1)
722 C_LDLO REG6,UNITM1(15)(a1)
723 C_LDLO REG7,UNITM1(16)(a1)
724 PREFETCH_FOR_LOAD (5, a1)
735 PTR_ADDIU a1,a1,UNIT(16) /* adding 64/128 to src */
744 PREFETCH_FOR_LOAD (0, a1)
749 C_LDHI t0,UNIT(0)(a1)
750 C_LDHI t1,UNIT(1)(a1)
751 C_LDHI REG2,UNIT(2)(a1)
752 C_LDHI REG3,UNIT(3)(a1)
753 C_LDHI REG4,UNIT(4)(a1)
754 C_LDHI REG5,UNIT(5)(a1)
755 C_LDHI REG6,UNIT(6)(a1)
756 C_LDHI REG7,UNIT(7)(a1)
757 C_LDLO t0,UNITM1(1)(a1)
758 C_LDLO t1,UNITM1(2)(a1)
759 C_LDLO REG2,UNITM1(3)(a1)
760 C_LDLO REG3,UNITM1(4)(a1)
761 C_LDLO REG4,UNITM1(5)(a1)
762 C_LDLO REG5,UNITM1(6)(a1)
763 C_LDLO REG6,UNITM1(7)(a1)
764 C_LDLO REG7,UNITM1(8)(a1)
765 PTR_ADDIU a1,a1,UNIT(8)
787 C_LDHI v1,UNIT(0)(a1)
788 C_LDLO v1,UNITM1(1)(a1)
790 PTR_ADDIU a1,a1,UNIT(1)
799 lb v1,0(a1)
801 PTR_ADDIU a1,a1,1
825 PTR_SUBU REG2, a1, t8; /* REG2 is the aligned src address. */ \
826 PTR_ADDU a1, a1, a3; /* a1 is addr of source after word loop. */ \