Lines Matching refs:code

28 @code{__ppc_get_timebase} uses the processor's time base facility directly
88 @code{__ppc_set_ppr_med} (medium -- default), @code{__ppc_set_ppc_low} (low)
89 and @code{__ppc_set_ppc_med_low} (medium low).  More information
134 @code{SYS_RISCV_FLUSH_ICACHE_LOCAL} bit allows users to indicate that enforcing
168 @code{ACPI} -- Thermal Monitor and Software Controlled Clock Facilities.
171 @code{ADX} -- ADX instruction extensions.
174 @code{APIC} -- APIC On-Chip.
177 @code{AES} -- The AES instruction extensions.
180 @code{AESKLE} -- AES Key Locker instructions are enabled by OS.
183 @code{AMD_IBPB} -- Indirect branch predictor barrier (IBPB) for AMD cpus.
186 @code{AMD_IBRS} -- Indirect branch restricted speculation (IBPB) for AMD cpus.
189 @code{AMD_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus.
192 @code{AMD_STIBP} -- Single thread indirect branch predictors (STIBP) for AMD cpus.
195 @code{AMD_VIRT_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus (older systems).
198 @code{AMX_BF16} -- Tile computational operations on bfloat16 numbers.
201 @code{AMX_INT8} -- Tile computational operations on 8-bit numbers.
204 @code{AMX_TILE} -- Tile architecture.
207 @code{ARCH_CAPABILITIES} -- IA32_ARCH_CAPABILITIES MSR.
210 @code{AVX} -- The AVX instruction extensions.
213 @code{AVX2} -- The AVX2 instruction extensions.
216 @code{AVX_VNNI} -- The AVX-VNNI instruction extensions.
219 @code{AVX512_4FMAPS} -- The AVX512_4FMAPS instruction extensions.
222 @code{AVX512_4VNNIW} -- The AVX512_4VNNIW instruction extensions.
225 @code{AVX512_BF16} -- The AVX512_BF16 instruction extensions.
228 @code{AVX512_BITALG} -- The AVX512_BITALG instruction extensions.
231 @code{AVX512_FP16} -- The AVX512_FP16 instruction extensions.
234 @code{AVX512_IFMA} -- The AVX512_IFMA instruction extensions.
237 @code{AVX512_VBMI} -- The AVX512_VBMI instruction extensions.
240 @code{AVX512_VBMI2} -- The AVX512_VBMI2 instruction extensions.
243 @code{AVX512_VNNI} -- The AVX512_VNNI instruction extensions.
246 @code{AVX512_VP2INTERSECT} -- The AVX512_VP2INTERSECT instruction
250 @code{AVX512_VPOPCNTDQ} -- The AVX512_VPOPCNTDQ instruction extensions.
253 @code{AVX512BW} -- The AVX512BW instruction extensions.
256 @code{AVX512CD} -- The AVX512CD instruction extensions.
259 @code{AVX512ER} -- The AVX512ER instruction extensions.
262 @code{AVX512DQ} -- The AVX512DQ instruction extensions.
265 @code{AVX512F} -- The AVX512F instruction extensions.
268 @code{AVX512PF} -- The AVX512PF instruction extensions.
271 @code{AVX512VL} -- The AVX512VL instruction extensions.
274 @code{BMI1} -- BMI1 instructions.
277 @code{BMI2} -- BMI2 instructions.
280 @code{CLDEMOTE} -- CLDEMOTE instruction.
283 @code{CLFLUSHOPT} -- CLFLUSHOPT instruction.
286 @code{CLFSH} -- CLFLUSH instruction.
289 @code{CLWB} -- CLWB instruction.
292 @code{CMOV} -- Conditional Move instructions.
295 @code{CMPXCHG16B} -- CMPXCHG16B instruction.
298 @code{CNXT_ID} -- L1 Context ID.
301 @code{CORE_CAPABILITIES} -- IA32_CORE_CAPABILITIES MSR.
304 @code{CX8} -- CMPXCHG8B instruction.
307 @code{DCA} -- Data prefetch from a memory mapped device.
310 @code{DE} -- Debugging Extensions.
313 @code{DEPR_FPU_CS_DS} -- Deprecates FPU CS and FPU DS values.
316 @code{DS} -- Debug Store.
319 @code{DS_CPL} -- CPL Qualified Debug Store.
322 @code{DTES64} -- 64-bit DS Area.
325 @code{EIST} -- Enhanced Intel SpeedStep technology.
328 @code{ENQCMD} -- Enqueue Stores instructions.
331 @code{ERMS} -- Enhanced REP MOVSB/STOSB.
334 @code{F16C} -- 16-bit floating-point conversion instructions.
337 @code{FMA} -- FMA extensions using YMM state.
340 @code{FMA4} -- FMA4 instruction extensions.
343 @code{FPU} -- X87 Floating Point Unit On-Chip.
346 @code{FSGSBASE} -- RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instructions.
349 @code{FSRCS} -- Fast Short REP CMP and SCA.
352 @code{FSRM} -- Fast Short REP MOV.
355 @code{FSRS} -- Fast Short REP STO.
358 @code{FXSR} -- FXSAVE and FXRSTOR instructions.
361 @code{FZLRM} -- Fast Zero-Length REP MOV.
364 @code{GFNI} -- GFNI instruction extensions.
367 @code{HLE} -- HLE instruction extensions.
370 @code{HTT} -- Max APIC IDs reserved field is Valid.
373 @code{HRESET} -- History reset.
376 @code{HYBRID} -- Hybrid processor.
379 @code{IBRS_IBPB} -- Indirect branch restricted speculation (IBRS) and
383 @code{IBT} -- Intel Indirect Branch Tracking instruction extensions.
386 @code{INVARIANT_TSC} -- Invariant TSC.
389 @code{INVPCID} -- INVPCID instruction.
392 @code{KL} -- AES Key Locker instructions.
395 @code{LAM} -- Linear Address Masking.
398 @code{L1D_FLUSH} -- IA32_FLUSH_CMD MSR.
401 @code{LAHF64_SAHF64} -- LAHF/SAHF available in 64-bit mode.
404 @code{LM} -- Long mode.
407 @code{LWP} -- Lightweight profiling.
410 @code{LZCNT} -- LZCNT instruction.
413 @code{MCA} -- Machine Check Architecture.
416 @code{MCE} -- Machine Check Exception.
419 @code{MD_CLEAR} -- MD_CLEAR.
422 @code{MMX} -- Intel MMX Technology.
425 @code{MONITOR} --  MONITOR/MWAIT instructions.
428 @code{MOVBE} -- MOVBE instruction.
431 @code{MOVDIRI} -- MOVDIRI instruction.
434 @code{MOVDIR64B} -- MOVDIR64B instruction.
437 @code{MPX} -- Intel Memory Protection Extensions.
440 @code{MSR} -- Model Specific Registers RDMSR and WRMSR instructions.
443 @code{MTRR} -- Memory Type Range Registers.
446 @code{NX} -- No-execute page protection.
449 @code{OSPKE} -- OS has set CR4.PKE to enable protection keys.
452 @code{OSXSAVE} -- The OS has set CR4.OSXSAVE[bit 18] to enable
457 @code{PAE} -- Physical Address Extension.
460 @code{PAGE1GB} -- 1-GByte page.
463 @code{PAT} -- Page Attribute Table.
466 @code{PBE} -- Pending Break Enable.
469 @code{PCID} -- Process-context identifiers.
472 @code{PCLMULQDQ} -- PCLMULQDQ instruction.
475 @code{PCONFIG} -- PCONFIG instruction.
478 @code{PDCM} -- Perfmon and Debug Capability.
481 @code{PGE} -- Page Global Bit.
484 @code{PKS} -- Protection keys for supervisor-mode pages.
487 @code{PKU} -- Protection keys for user-mode pages.
490 @code{POPCNT} -- POPCNT instruction.
493 @code{PREFETCHW} -- PREFETCHW instruction.
496 @code{PREFETCHWT1} -- PREFETCHWT1 instruction.
499 @code{PSE} -- Page Size Extension.
502 @code{PSE_36} -- 36-Bit Page Size Extension.
505 @code{PSN} -- Processor Serial Number.
508 @code{PTWRITE} -- PTWRITE instruction.
511 @code{RDPID} -- RDPID instruction.
514 @code{RDRAND} -- RDRAND instruction.
517 @code{RDSEED} -- RDSEED instruction.
520 @code{RDT_A} -- Intel Resource Director Technology (Intel RDT) Allocation
524 @code{RDT_M} -- Intel Resource Director Technology (Intel RDT) Monitoring
528 @code{RDTSCP} -- RDTSCP instruction.
531 @code{RTM} -- RTM instruction extensions.
534 @code{RTM_ALWAYS_ABORT} -- Transactions always abort, making RTM unusable.
537 @code{SDBG} -- IA32_DEBUG_INTERFACE MSR for silicon debug.
540 @code{SEP} -- SYSENTER and SYSEXIT instructions.
543 @code{SERIALIZE} -- SERIALIZE instruction.
546 @code{SGX} -- Intel Software Guard Extensions.
549 @code{SGX_LC} -- SGX Launch Configuration.
552 @code{SHA} -- SHA instruction extensions.
555 @code{SHSTK} -- Intel Shadow Stack instruction extensions.
558 @code{SMAP} -- Supervisor-Mode Access Prevention.
561 @code{SMEP} -- Supervisor-Mode Execution Prevention.
564 @code{SMX} -- Safer Mode Extensions.
567 @code{SS} -- Self Snoop.
570 @code{SSBD} -- Speculative Store Bypass Disable (SSBD).
573 @code{SSE} -- Streaming SIMD Extensions.
576 @code{SSE2} -- Streaming SIMD Extensions 2.
579 @code{SSE3} -- Streaming SIMD Extensions 3.
582 @code{SSE4_1} -- Streaming SIMD Extensions 4.1.
585 @code{SSE4_2} -- Streaming SIMD Extensions 4.2.
588 @code{SSE4A} -- SSE4A instruction extensions.
591 @code{SSSE3} -- Supplemental Streaming SIMD Extensions 3.
594 @code{STIBP} -- Single thread indirect branch predictors (STIBP).
597 @code{SVM} -- Secure Virtual Machine.
600 @code{SYSCALL_SYSRET} -- SYSCALL/SYSRET instructions.
603 @code{TBM} -- Trailing bit manipulation instructions.
606 @code{TM} -- Thermal Monitor.
609 @code{TM2} -- Thermal Monitor 2.
612 @code{TRACE} -- Intel Processor Trace.
615 @code{TSC} -- Time Stamp Counter.  RDTSC instruction.
618 @code{TSC_ADJUST} -- IA32_TSC_ADJUST MSR.
621 @code{TSC_DEADLINE} -- Local APIC timer supports one-shot operation
625 @code{TSXLDTRK} -- TSXLDTRK instructions.
628 @code{UINTR} -- User interrupts.
631 @code{UMIP} -- User-mode instruction prevention.
634 @code{VAES} -- VAES instruction extensions.
637 @code{VME} -- Virtual 8086 Mode Enhancements.
640 @code{VMX} -- Virtual Machine Extensions.
643 @code{VPCLMULQDQ} -- VPCLMULQDQ instruction.
646 @code{WAITPKG} -- WAITPKG instruction extensions.
649 @code{WBNOINVD} -- WBINVD/WBNOINVD instructions.
652 @code{WIDE_KL} -- AES wide Key Locker instructions.
655 @code{X2APIC} -- x2APIC.
658 @code{XFD} -- Extended Feature Disable (XFD).
661 @code{XGETBV_ECX_1} -- XGETBV with ECX = 1.
664 @code{XOP} -- XOP instruction extensions.
667 @code{XSAVE} -- The XSAVE/XRSTOR processor extended states feature, the
671 @code{XSAVEC} -- XSAVEC instruction.
674 @code{XSAVEOPT} -- XSAVEOPT instruction.
677 @code{XSAVES} -- XSAVES/XRSTORS instructions.
680 @code{XTPRUPDCTRL} -- xTPR Update Control.
684 You could query if a processor supports @code{AVX} with:
696 and if @code{AVX} is active and may be used with: