Lines Matching refs:u8
11 pub const ATA_CMD_READ_DMA_EXT: u8 = 0x25; // 读操作，并且退出
12 pub const ATA_CMD_WRITE_DMA_EXT: u8 = 0x35; // 写操作，并且退出
14 pub const ATA_CMD_IDENTIFY: u8 = 0xEC;
16 pub const ATA_CMD_IDENTIFY_PACKET: u8 = 0xA1;
18 pub const ATA_CMD_PACKET: u8 = 0xA0;
19 pub const ATA_DEV_BUSY: u8 = 0x80;
20 pub const ATA_DEV_DRQ: u8 = 0x08;
83 pub _rsv: [u8; 116], // 0x2C - 0x9F, Reserved
84 pub vendor: [u8; 96], // 0xA0 - 0xFF, Vendor specific registers
103 pub cfis: [u8; 64], // Command FIS
105 pub acmd: [u8; 16], // ATAPI command, 12 or 16 bytes
107 _rsv: [u8; 48], // Reserved
118 pub cfl: u8,
120 pub _pm: u8, // Reset - 0x80, bist: 0x40, clear busy on ok: 0x20, port multiplier
269 #[repr(u8)]
294 pub fis_type: u8, // FIS_TYPE_REG_H2D
296 pub pm: u8, // Port multiplier, 1: Command, 0: Control
300 pub command: u8, // Command register
301 pub featurel: u8, // Feature register, 7:0
304 pub lba0: u8, // LBA low register, 7:0
305 pub lba1: u8, // LBA mid register, 15:8
306 pub lba2: u8, // LBA high register, 23:16
307 pub device: u8, // Device register
310 pub lba3: u8, // LBA register, 31:24
311 pub lba4: u8, // LBA register, 39:32
312 pub lba5: u8, // LBA register, 47:40
313 pub featureh: u8, // Feature register, 15:8
316 pub countl: u8, // Count register, 7:0
317 pub counth: u8, // Count register, 15:8
318 pub icc: u8, // Isochronous command completion
319 pub control: u8, // Control register
322 pub rsv1: [u8; 4], // Reserved
329 pub fis_type: u8, // FIS_TYPE_REG_D2H
331 pub pm: u8, // Port multiplier, Interrupt bit: 2
333 pub status: u8, // Status register
334 pub error: u8, // Error register
337 pub lba0: u8, // LBA low register, 7:0
338 pub lba1: u8, // LBA mid register, 15:8
339 pub lba2: u8, // LBA high register, 23:16
340 pub device: u8, // Device register
343 pub lba3: u8, // LBA register, 31:24
344 pub lba4: u8, // LBA register, 39:32
345 pub lba5: u8, // LBA register, 47:40
346 pub rsv2: u8, // Reserved
349 pub countl: u8, // Count register, 7:0
350 pub counth: u8, // Count register, 15:8
351 pub rsv3: [u8; 2], // Reserved
354 pub rsv4: [u8; 4], // Reserved
361 pub fis_type: u8, // FIS_TYPE_DATA
363 pub pm: u8, // Port multiplier
365 pub rsv1: [u8; 2], // Reserved
368 pub data: [u8; 252], // Payload
375 pub fis_type: u8, // FIS_TYPE_PIO_SETUP
377 pub pm: u8, // Port multiplier, direction: 4 - device to host, interrupt: 2
379 pub status: u8, // Status register
380 pub error: u8, // Error register
383 pub lba0: u8, // LBA low register, 7:0
384 pub lba1: u8, // LBA mid register, 15:8
385 pub lba2: u8, // LBA high register, 23:16
386 pub device: u8, // Device register
389 pub lba3: u8, // LBA register, 31:24
390 pub lba4: u8, // LBA register, 39:32
391 pub lba5: u8, // LBA register, 47:40
392 pub rsv2: u8, // Reserved
395 pub countl: u8, // Count register, 7:0
396 pub counth: u8, // Count register, 15:8
397 pub rsv3: u8, // Reserved
398 pub e_status: u8, // New value of status register
402 pub rsv4: [u8; 2], // Reserved
409 pub fis_type: u8, // FIS_TYPE_DMA_SETUP
411 pub pm: u8, // Port multiplier, direction: 4 - device to host, interrupt: 2, auto-activate: 1
413 pub rsv1: [u8; 2], // Reserved