Lines Matching refs:REG_TABLE
144 assert!(!(0x3..REG_TABLE).contains(®)); in read()
157 assert!(!(0x1..REG_TABLE).contains(®)); in write()
164 self.write(REG_TABLE + 2 * rte_index, vector as u32 | flags.bits()); in write_rte()
165 self.write(REG_TABLE + 2 * rte_index + 1, (dest as u32) << 24); in write_rte()
172 let mut val = unsafe { self.read(REG_TABLE + 2 * rte_index) }; in enable()
174 unsafe { self.write(REG_TABLE + 2 * rte_index, val) }; in enable()
178 let reg = REG_TABLE + 2 * rte_index; in disable()
237 unsafe { self.read(REG_TABLE + 2 * irq).get_bits(0..8) as u8 } in irq_vector()
243 let mut old = unsafe { self.read(REG_TABLE + 2 * irq) }; in set_irq_vector()
249 self.write(REG_TABLE + 2 * irq, *old.set_bits(0..8, vector as u32)); in set_irq_vector()
274 let data = unsafe { self.read(REG_TABLE + 2 * rte_index) }; in pending()
304 const REG_TABLE: u8 = 0x10; constant