31 enum OperandSize {  enum
248     fn emit_load(&self, mem: &mut JitMemory, size: OperandSize, src: u8, dst: u8, offset: i32) {  in emit_load()  argument
250             OperandSize::S64 => 1,  in emit_load()
256             OperandSize::S8 => {  in emit_load()
261             OperandSize::S16 => {  in emit_load()
266             OperandSize::S32 | OperandSize::S64 => {  in emit_load()
288     fn emit_store(&self, mem: &mut JitMemory, size: OperandSize, src: u8, dst: u8, offset: i32) {  in emit_store()  argument
290             OperandSize::S16 => self.emit1(mem, 0x66), // 16-bit override  in emit_store()
294             OperandSize::S8 => (true, false, 0),  in emit_store()
295             OperandSize::S64 => (false, true, 1),  in emit_store()
306             OperandSize::S8 => self.emit1(mem, 0x88),  in emit_store()
316         size: OperandSize,  in emit_store_imm32()  argument
322             OperandSize::S16 => self.emit1(mem, 0x66), // 16-bit override  in emit_store_imm32()
326             OperandSize::S64 => self.emit_basic_rex(mem, 1, 0, dst),  in emit_store_imm32()
330             OperandSize::S8 => self.emit1(mem, 0xc6),  in emit_store_imm32()
335             OperandSize::S8 => self.emit1(mem, imm as u8),  in emit_store_imm32()
336             OperandSize::S16 => self.emit2(mem, imm as u16),  in emit_store_imm32()
514                 self.emit_store(mem, OperandSize::S64, RDX, R8, 0); // set mem at mbuff + mem_offset  in jit_compile()
516                 self.emit_load(mem, OperandSize::S64, RDX, R8, 0); // load mem into R8  in jit_compile()
519                 self.emit_store(mem, OperandSize::S64, R8, R9, 0); // store mem_end  in jit_compile()
549                 ebpf::LD_ABS_B => self.emit_load(mem, OperandSize::S8, R10, RAX, insn.imm),  in jit_compile()
550                 ebpf::LD_ABS_H => self.emit_load(mem, OperandSize::S16, R10, RAX, insn.imm),  in jit_compile()
551                 ebpf::LD_ABS_W => self.emit_load(mem, OperandSize::S32, R10, RAX, insn.imm),  in jit_compile()
552                 ebpf::LD_ABS_DW => self.emit_load(mem, OperandSize::S64, R10, RAX, insn.imm),  in jit_compile()
556                     self.emit_load(mem, OperandSize::S8, R11, RAX, insn.imm); // ld R0, mem[src+imm]  in jit_compile()
561 …                  self.emit_load(mem, OperandSize::S16, R11, RAX, insn.imm); // ld R0, mem[src+imm]  in jit_compile()
566 …                  self.emit_load(mem, OperandSize::S32, R11, RAX, insn.imm); // ld R0, mem[src+imm]  in jit_compile()
571 …                  self.emit_load(mem, OperandSize::S64, R11, RAX, insn.imm); // ld R0, mem[src+imm]  in jit_compile()
582                 ebpf::LD_B_REG => self.emit_load(mem, OperandSize::S8, src, dst, insn.off as i32),  in jit_compile()
583                 ebpf::LD_H_REG => self.emit_load(mem, OperandSize::S16, src, dst, insn.off as i32),  in jit_compile()
584                 ebpf::LD_W_REG => self.emit_load(mem, OperandSize::S32, src, dst, insn.off as i32),  in jit_compile()
585                 ebpf::LD_DW_REG => self.emit_load(mem, OperandSize::S64, src, dst, insn.off as i32),  in jit_compile()
589                     self.emit_store_imm32(mem, OperandSize::S8, dst, insn.off as i32, insn.imm)  in jit_compile()
592                     self.emit_store_imm32(mem, OperandSize::S16, dst, insn.off as i32, insn.imm)  in jit_compile()
595                     self.emit_store_imm32(mem, OperandSize::S32, dst, insn.off as i32, insn.imm)  in jit_compile()
598                     self.emit_store_imm32(mem, OperandSize::S64, dst, insn.off as i32, insn.imm)  in jit_compile()
602                 ebpf::ST_B_REG => self.emit_store(mem, OperandSize::S8, src, dst, insn.off as i32),  in jit_compile()
603                 ebpf::ST_H_REG => self.emit_store(mem, OperandSize::S16, src, dst, insn.off as i32),  in jit_compile()
604                 ebpf::ST_W_REG => self.emit_store(mem, OperandSize::S32, src, dst, insn.off as i32),  in jit_compile()
606                     self.emit_store(mem, OperandSize::S64, src, dst, insn.off as i32)  in jit_compile()