Lines Matching refs:header
20 list_add(pci_device_structure_list, &(ret->header.list)); \
25 list_init(&(ret->header.list)); \
26 pci_device_structure_list = &(ret->header.list); \
88 static void pci_read_general_device_header(struct pci_device_structure_general_device_t *header, uc… in pci_read_general_device_header() argument
91 header->BAR0 = pci_read_config(bus, slot, func, 0x10); in pci_read_general_device_header()
92 header->BAR1 = pci_read_config(bus, slot, func, 0x14); in pci_read_general_device_header()
93 header->BAR2 = pci_read_config(bus, slot, func, 0x18); in pci_read_general_device_header()
94 header->BAR3 = pci_read_config(bus, slot, func, 0x1c); in pci_read_general_device_header()
95 header->BAR4 = pci_read_config(bus, slot, func, 0x20); in pci_read_general_device_header()
96 header->BAR5 = pci_read_config(bus, slot, func, 0x24); in pci_read_general_device_header()
97 header->Cardbus_CIS_Pointer = pci_read_config(bus, slot, func, 0x28); in pci_read_general_device_header()
100 header->Subsystem_Vendor_ID = tmp32 & 0xffff; in pci_read_general_device_header()
101 header->Subsystem_ID = (tmp32 >> 16) & 0xffff; in pci_read_general_device_header()
103 header->Expansion_ROM_base_address = pci_read_config(bus, slot, func, 0x30); in pci_read_general_device_header()
106 header->Capabilities_Pointer = tmp32 & 0xff; in pci_read_general_device_header()
107 header->reserved0 = (tmp32 >> 8) & 0xff; in pci_read_general_device_header()
108 header->reserved1 = (tmp32 >> 16) & 0xffff; in pci_read_general_device_header()
110 header->reserved2 = pci_read_config(bus, slot, func, 0x38); in pci_read_general_device_header()
113 header->Interrupt_Line = tmp32 & 0xff; in pci_read_general_device_header()
114 header->Interrupt_PIN = (tmp32 >> 8) & 0xff; in pci_read_general_device_header()
115 header->Min_Grant = (tmp32 >> 16) & 0xff; in pci_read_general_device_header()
116 header->Max_Latency = (tmp32 >> 24) & 0xff; in pci_read_general_device_header()
127 …ci_to_pci_bridge_header(struct pci_device_structure_pci_to_pci_bridge_t *header, uchar bus, uchar … in pci_read_pci_to_pci_bridge_header() argument
130 header->BAR0 = pci_read_config(bus, slot, func, 0x10); in pci_read_pci_to_pci_bridge_header()
131 header->BAR1 = pci_read_config(bus, slot, func, 0x14); in pci_read_pci_to_pci_bridge_header()
135 header->Primary_Bus_Number = tmp32 & 0xff; in pci_read_pci_to_pci_bridge_header()
136 header->Secondary_Bus_Number = (tmp32 >> 8) & 0xff; in pci_read_pci_to_pci_bridge_header()
137 header->Subordinate_Bus_Number = (tmp32 >> 16) & 0xff; in pci_read_pci_to_pci_bridge_header()
138 header->Secondary_Latency_Timer = (tmp32 >> 24) & 0xff; in pci_read_pci_to_pci_bridge_header()
141 header->io_base = tmp32 & 0xff; in pci_read_pci_to_pci_bridge_header()
142 header->io_limit = (tmp32 >> 8) & 0xff; in pci_read_pci_to_pci_bridge_header()
143 header->Secondary_Status = (tmp32 >> 16) & 0xffff; in pci_read_pci_to_pci_bridge_header()
146 header->Memory_Base = tmp32 & 0xffff; in pci_read_pci_to_pci_bridge_header()
147 header->Memory_Limit = (tmp32 >> 16) & 0xffff; in pci_read_pci_to_pci_bridge_header()
150 header->Prefetchable_Memory_Base = tmp32 & 0xffff; in pci_read_pci_to_pci_bridge_header()
151 header->Prefetchable_Memory_Limit = (tmp32 >> 16) & 0xffff; in pci_read_pci_to_pci_bridge_header()
153 header->Prefetchable_Base_Upper_32_Bits = pci_read_config(bus, slot, func, 0x28); in pci_read_pci_to_pci_bridge_header()
154 header->Prefetchable_Limit_Upper_32_Bits = pci_read_config(bus, slot, func, 0x2c); in pci_read_pci_to_pci_bridge_header()
157 header->io_Base_Upper_16_Bits = tmp32 & 0xffff; in pci_read_pci_to_pci_bridge_header()
158 header->io_Limit_Upper_16_Bits = (tmp32 >> 16) & 0xffff; in pci_read_pci_to_pci_bridge_header()
161 header->Capability_Pointer = tmp32 & 0xff; in pci_read_pci_to_pci_bridge_header()
162 header->reserved0 = (tmp32 >> 8) & 0xff; in pci_read_pci_to_pci_bridge_header()
163 header->reserved1 = (tmp32 >> 16) & 0xffff; in pci_read_pci_to_pci_bridge_header()
165 header->Expansion_ROM_base_address = pci_read_config(bus, slot, func, 0x38); in pci_read_pci_to_pci_bridge_header()
168 header->Interrupt_Line = tmp32 & 0xff; in pci_read_pci_to_pci_bridge_header()
169 header->Interrupt_PIN = (tmp32 >> 8) & 0xff; in pci_read_pci_to_pci_bridge_header()
170 header->Bridge_Control = (tmp32 >> 16) & 0xffff; in pci_read_pci_to_pci_bridge_header()
181 …rdbus_bridge_header(struct pci_device_structure_pci_to_cardbus_bridge_t *header, uchar bus, uchar … in pci_read_pci_to_cardbus_bridge_header() argument
185 header->CardBus_Socket_ExCa_base_address = pci_read_config(bus, slot, func, 0x10); in pci_read_pci_to_cardbus_bridge_header()
188 header->Offset_of_capabilities_list = tmp32 & 0xff; in pci_read_pci_to_cardbus_bridge_header()
189 header->Reserved = (tmp32 >> 8) & 0xff; in pci_read_pci_to_cardbus_bridge_header()
190 header->Secondary_status = (tmp32 >> 16) & 0xff; in pci_read_pci_to_cardbus_bridge_header()
193 header->PCI_bus_number = tmp32 & 0xff; in pci_read_pci_to_cardbus_bridge_header()
194 header->CardBus_bus_number = (tmp32 >> 8) & 0xff; in pci_read_pci_to_cardbus_bridge_header()
195 header->Subordinate_bus_number = (tmp32 >> 16) & 0xff; in pci_read_pci_to_cardbus_bridge_header()
196 header->CardBus_latency_timer = (tmp32 >> 24) & 0xff; in pci_read_pci_to_cardbus_bridge_header()
198 header->Memory_Base_Address0 = pci_read_config(bus, slot, func, 0x1c); in pci_read_pci_to_cardbus_bridge_header()
199 header->Memory_Limit0 = pci_read_config(bus, slot, func, 0x20); in pci_read_pci_to_cardbus_bridge_header()
200 header->Memory_Base_Address1 = pci_read_config(bus, slot, func, 0x24); in pci_read_pci_to_cardbus_bridge_header()
201 header->Memory_Limit1 = pci_read_config(bus, slot, func, 0x28); in pci_read_pci_to_cardbus_bridge_header()
203 header->IO_Base_Address0 = pci_read_config(bus, slot, func, 0x2c); in pci_read_pci_to_cardbus_bridge_header()
204 header->IO_Limit0 = pci_read_config(bus, slot, func, 0x30); in pci_read_pci_to_cardbus_bridge_header()
205 header->IO_Base_Address1 = pci_read_config(bus, slot, func, 0x34); in pci_read_pci_to_cardbus_bridge_header()
206 header->IO_Limit1 = pci_read_config(bus, slot, func, 0x38); in pci_read_pci_to_cardbus_bridge_header()
209 header->Interrupt_Line = tmp32 & 0xff; in pci_read_pci_to_cardbus_bridge_header()
210 header->Interrupt_PIN = (tmp32 >> 8) & 0xff; in pci_read_pci_to_cardbus_bridge_header()
211 header->Bridge_Control = (tmp32 >> 16) & 0xffff; in pci_read_pci_to_cardbus_bridge_header()
214 header->Subsystem_Device_ID = tmp32 & 0xffff; in pci_read_pci_to_cardbus_bridge_header()
215 header->Subsystem_Vendor_ID = (tmp32 >> 16) & 0xffff; in pci_read_pci_to_cardbus_bridge_header()
217 header->PC_Card_legacy_mode_base_address_16_bit = pci_read_config(bus, slot, func, 0x44); in pci_read_pci_to_cardbus_bridge_header()
311 …struct pci_device_structure_header_t *header = pci_read_header(&header_type, bus, device, function… in pci_checkFunction() local
321 if ((header->Class_code == 0x6) && (header->SubClass == 0x4)) in pci_checkFunction()
323 …uint8_t SecondaryBus = ((struct pci_device_structure_pci_to_pci_bridge_t *)header)->Secondary_Bus_… in pci_checkFunction()
332 …struct pci_device_structure_header_t *header = pci_read_header(&header_type, bus, device, 0, false… in pci_checkDevice() local
344 uint16_t vendorID = header->Vendor_ID; in pci_checkDevice()
348 kfree(header); in pci_checkDevice()
353 header_type = header->HeaderType; in pci_checkDevice()
371 kfree(header); in pci_checkDevice()
391 struct pci_device_structure_header_t *header = pci_read_header(&header_type, 0, 0, 0, false); in pci_checkAllBuses() local
400 header_type = header->HeaderType; in pci_checkAllBuses()
415 if (WARN_ON(header->Vendor_ID != 0xffff)) // @todo 这里的判断条件可能有点问题 in pci_checkAllBuses()
426 kfree(header); in pci_checkAllBuses()