590     pub fn read_config(&self, bus_device_function: BusDeviceFunction, register_offset: u16) -> u32 {  in read_config()  method
633     let result = PciArch::read_config(&bus_device_function, STATUS_COMMAND_OFFSET);  in capabilities_offset()
636         let cap_pointer = PciArch::read_config(&bus_device_function, 0x34) as u8 & 0xFC;  in capabilities_offset()
652     let result = PciArch::read_config(&bus_device_function, 0x00);  in pci_read_header()
656     let result = PciArch::read_config(&bus_device_function, 0x04);  in pci_read_header()
660     let result = PciArch::read_config(&bus_device_function, 0x08);  in pci_read_header()
666     let result = PciArch::read_config(&bus_device_function, 0x0c);  in pci_read_header()
736     let cardbus_cis_pointer = PciArch::read_config(bus_device_function, 0x28);  in pci_read_general_device_header()
738     let result = PciArch::read_config(bus_device_function, 0x2c);  in pci_read_general_device_header()
742     let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x30);  in pci_read_general_device_header()
744     let result = PciArch::read_config(bus_device_function, 0x34);  in pci_read_general_device_header()
749     let reserved2 = PciArch::read_config(bus_device_function, 0x38);  in pci_read_general_device_header()
751     let result = PciArch::read_config(bus_device_function, 0x3c);  in pci_read_general_device_header()
783     let bar0 = PciArch::read_config(bus_device_function, 0x10);  in pci_read_pci_to_pci_bridge_header()
784     let bar1 = PciArch::read_config(bus_device_function, 0x14);  in pci_read_pci_to_pci_bridge_header()
786     let result = PciArch::read_config(bus_device_function, 0x18);  in pci_read_pci_to_pci_bridge_header()
793     let result = PciArch::read_config(bus_device_function, 0x1c);  in pci_read_pci_to_pci_bridge_header()
798     let result = PciArch::read_config(bus_device_function, 0x20);  in pci_read_pci_to_pci_bridge_header()
802     let result = PciArch::read_config(bus_device_function, 0x24);  in pci_read_pci_to_pci_bridge_header()
806     let prefetchable_base_upper_32_bits = PciArch::read_config(bus_device_function, 0x28);  in pci_read_pci_to_pci_bridge_header()
807     let prefetchable_limit_upper_32_bits = PciArch::read_config(bus_device_function, 0x2c);  in pci_read_pci_to_pci_bridge_header()
809     let result = PciArch::read_config(bus_device_function, 0x30);  in pci_read_pci_to_pci_bridge_header()
813     let result = PciArch::read_config(bus_device_function, 0x34);  in pci_read_pci_to_pci_bridge_header()
818     let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x38);  in pci_read_pci_to_pci_bridge_header()
820     let result = PciArch::read_config(bus_device_function, 0x3c);  in pci_read_pci_to_pci_bridge_header()
862     let cardbus_socket_ex_ca_base_address = PciArch::read_config(busdevicefunction, 0x10);  in pci_read_pci_to_cardbus_bridge_header()
864     let result = PciArch::read_config(busdevicefunction, 0x14);  in pci_read_pci_to_cardbus_bridge_header()
869     let result = PciArch::read_config(busdevicefunction, 0x18);  in pci_read_pci_to_cardbus_bridge_header()
875     let memory_base_address0 = PciArch::read_config(busdevicefunction, 0x1c);  in pci_read_pci_to_cardbus_bridge_header()
876     let memory_limit0 = PciArch::read_config(busdevicefunction, 0x20);  in pci_read_pci_to_cardbus_bridge_header()
877     let memory_base_address1 = PciArch::read_config(busdevicefunction, 0x24);  in pci_read_pci_to_cardbus_bridge_header()
878     let memory_limit1 = PciArch::read_config(busdevicefunction, 0x28);  in pci_read_pci_to_cardbus_bridge_header()
880     let io_base_address0 = PciArch::read_config(busdevicefunction, 0x2c);  in pci_read_pci_to_cardbus_bridge_header()
881     let io_limit0 = PciArch::read_config(busdevicefunction, 0x30);  in pci_read_pci_to_cardbus_bridge_header()
882     let io_base_address1 = PciArch::read_config(busdevicefunction, 0x34);  in pci_read_pci_to_cardbus_bridge_header()
883     let io_limit1 = PciArch::read_config(busdevicefunction, 0x38);  in pci_read_pci_to_cardbus_bridge_header()
884     let result = PciArch::read_config(busdevicefunction, 0x3c);  in pci_read_pci_to_cardbus_bridge_header()
889     let result = PciArch::read_config(busdevicefunction, 0x40);  in pci_read_pci_to_cardbus_bridge_header()
893     let pc_card_legacy_mode_base_address_16_bit = PciArch::read_config(busdevicefunction, 0x44);  in pci_read_pci_to_cardbus_bridge_header()
1289         let bar_orig = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index);  in pci_bar_init()
1295         let size_mask = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index);  in pci_bar_init()
1319                     PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * (bar_index + 1));  in pci_bar_init()
1403         let capability_header = PciArch::read_config(&self.bus_device_function, offset);  in next()
1451         let capability_header = self.root.read_config(self.bus_device_function, offset);  in next()