Lines Matching refs:uint32_t
138 uint32_t data[1]; // Payload
198 uint32_t rsvd; // More reserved
201 uint32_t DMAbufOffset; // Byte offset into buffer. First 2 bits must be 0
204 uint32_t TransferCount; // Number of bytes to transfer. Bit 0 must be 0
207 uint32_t resvd; // Reserved
215 uint32_t is; // 0x10, interrupt status
216 uint32_t ie; // 0x14, interrupt enable
217 uint32_t cmd; // 0x18, command and status
218 uint32_t rsv0; // 0x1C, Reserved
219 uint32_t tfd; // 0x20, task file data
220 uint32_t sig; // 0x24, signature
221 uint32_t ssts; // 0x28, SATA status (SCR0:SStatus)
222 uint32_t sctl; // 0x2C, SATA control (SCR2:SControl)
223 uint32_t serr; // 0x30, SATA error (SCR1:SError)
224 uint32_t sact; // 0x34, SATA active (SCR3:SActive)
225 uint32_t ci; // 0x38, command issue
226 uint32_t sntf; // 0x3C, SATA notification (SCR4:SNotification)
227 uint32_t fbs; // 0x40, FIS-based switch control
228 uint32_t rsv1[11]; // 0x44 ~ 0x6F, Reserved
229 uint32_t vendor[4]; // 0x70 ~ 0x7F, vendor specific
234 uint32_t cap; // 0x00, Host capability
235 uint32_t ghc; // 0x04, Global host control
236 uint32_t is; // 0x08, Interrupt status
237 uint32_t pi; // 0x0C, Port implemented
238 uint32_t vs; // 0x10, Version
239 uint32_t ccc_ctl; // 0x14, Command completion coalescing control
240 uint32_t ccc_pts; // 0x18, Command completion coalescing ports
241 uint32_t em_loc; // 0x1C, Enclosure management location
242 uint32_t em_ctl; // 0x20, Enclosure management control
243 uint32_t cap2; // 0x24, Host capabilities extended
244 uint32_t bohc; // 0x28, BIOS/OS handoff control and status
299 volatile uint32_t prdbc; // Physical region descriptor byte count transferred
305 uint32_t rsv1[4]; // Reserved
311 uint32_t rsv0; // Reserved
314 uint32_t dbc : 22; // Byte count, 4M max
315 uint32_t rsv1 : 9; // Reserved
316 uint32_t i : 1; // Interrupt on completion
336 uint32_t type; // 设备类型