Lines Matching refs:uint8_t
59 uint8_t fis_type; // FIS_TYPE_REG_H2D
61 uint8_t pmport : 4; // Port multiplier
62 uint8_t rsv0 : 3; // Reserved
63 uint8_t c : 1; // 1: Command, 0: Control
65 uint8_t command; // Command register
66 uint8_t featurel; // Feature register, 7:0
69 uint8_t lba0; // LBA low register, 7:0
70 uint8_t lba1; // LBA mid register, 15:8
71 uint8_t lba2; // LBA high register, 23:16
72 uint8_t device; // Device register
75 uint8_t lba3; // LBA register, 31:24
76 uint8_t lba4; // LBA register, 39:32
77 uint8_t lba5; // LBA register, 47:40
78 uint8_t featureh; // Feature register, 15:8
81 uint8_t countl; // Count register, 7:0
82 uint8_t counth; // Count register, 15:8
83 uint8_t icc; // Isochronous command completion
84 uint8_t control; // Control register
87 uint8_t rsv1[4]; // Reserved
95 uint8_t fis_type; // FIS_TYPE_REG_D2H
97 uint8_t pmport : 4; // Port multiplier
98 uint8_t rsv0 : 2; // Reserved
99 uint8_t i : 1; // Interrupt bit
100 uint8_t rsv1 : 1; // Reserved
102 uint8_t status; // Status register
103 uint8_t error; // Error register
106 uint8_t lba0; // LBA low register, 7:0
107 uint8_t lba1; // LBA mid register, 15:8
108 uint8_t lba2; // LBA high register, 23:16
109 uint8_t device; // Device register
112 uint8_t lba3; // LBA register, 31:24
113 uint8_t lba4; // LBA register, 39:32
114 uint8_t lba5; // LBA register, 47:40
115 uint8_t rsv2; // Reserved
118 uint8_t countl; // Count register, 7:0
119 uint8_t counth; // Count register, 15:8
120 uint8_t rsv3[2]; // Reserved
123 uint8_t rsv4[4]; // Reserved
130 uint8_t fis_type; // FIS_TYPE_DATA
132 uint8_t pmport : 4; // Port multiplier
133 uint8_t rsv0 : 4; // Reserved
135 uint8_t rsv1[2]; // Reserved
145 uint8_t fis_type; // FIS_TYPE_PIO_SETUP
147 uint8_t pmport : 4; // Port multiplier
148 uint8_t rsv0 : 1; // Reserved
149 uint8_t d : 1; // Data transfer direction, 1 - device to host
150 uint8_t i : 1; // Interrupt bit
151 uint8_t rsv1 : 1;
153 uint8_t status; // Status register
154 uint8_t error; // Error register
157 uint8_t lba0; // LBA low register, 7:0
158 uint8_t lba1; // LBA mid register, 15:8
159 uint8_t lba2; // LBA high register, 23:16
160 uint8_t device; // Device register
163 uint8_t lba3; // LBA register, 31:24
164 uint8_t lba4; // LBA register, 39:32
165 uint8_t lba5; // LBA register, 47:40
166 uint8_t rsv2; // Reserved
169 uint8_t countl; // Count register, 7:0
170 uint8_t counth; // Count register, 15:8
171 uint8_t rsv3; // Reserved
172 uint8_t e_status; // New value of status register
176 uint8_t rsv4[2]; // Reserved
182 uint8_t fis_type; // FIS_TYPE_DMA_SETUP
184 uint8_t pmport : 4; // Port multiplier
185 uint8_t rsv0 : 1; // Reserved
186 uint8_t d : 1; // Data transfer direction, 1 - device to host
187 uint8_t i : 1; // Interrupt bit
188 uint8_t a : 1; // Auto-activate. Specifies if DMA Activate FIS is needed
190 uint8_t rsved[2]; // Reserved
247 uint8_t rsv[0xA0 - 0x2C];
250 uint8_t vendor[0x100 - 0xA0];
262 uint8_t pad0[4];
266 uint8_t pad1[12];
270 uint8_t pad2[4];
276 uint8_t ufis[64];
279 uint8_t rsv[0x100 - 0xA0];
285 uint8_t cfl : 5; // Command FIS length in DWORDS, 2 ~ 16
286 uint8_t a : 1; // ATAPI
287 uint8_t w : 1; // Write, 1: H2D, 0: D2H
288 uint8_t p : 1; // Prefetchable
290 uint8_t r : 1; // Reset
291 uint8_t b : 1; // BIST
292 uint8_t c : 1; // Clear busy upon R_OK
293 uint8_t rsv0 : 1; // Reserved
294 uint8_t pmp : 4; // Port multiplier port
322 uint8_t cfis[64]; // Command FIS
325 uint8_t acmd[16]; // ATAPI command, 12 or 16 bytes
328 uint8_t rsv[48]; // Reserved
358 uint8_t ahci_ctrl_num; // ahci控制器号， 默认应为0
359 uint8_t port_num; // ahci的设备端口号